/** @file\r
* Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
* This program and the accompanying materials\r
* are licensed and made available under the terms and conditions of the BSD License\r
//\r
\r
// Write VBAR - The Exception Vector table must be aligned to its requirement\r
- //TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64\r
- //ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+ // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r
+ // 'Align=4K' is defined into your FDF for this module.\r
+ ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
ArmWriteVBar ((UINTN)PeiVectorTable);\r
\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
// Migrate the temporary memory heap to permanent memory heap.\r
//\r
CopyMem (NewHeap, OldHeap, CopySize >> 1);\r
- \r
+\r
SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
\r
return EFI_SUCCESS;\r