\r
#include <AutoGen.h>\r
#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
+#include "SecInternal.h"\r
\r
.text\r
.align 3\r
\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
GCC_ASM_IMPORT(CEntryPoint)\r
GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)\r
GCC_ASM_IMPORT(ArmWriteVBar)\r
GCC_ASM_IMPORT(ArmReadMpidr)\r
GCC_ASM_IMPORT(SecVectorTable)\r
-\r
-#if (FixedPcdGet32(PcdMPCoreSupport))\r
-GCC_ASM_IMPORT(ArmIsScuEnable)\r
-#endif\r
+GCC_ASM_IMPORT(ArmCpuSynchronizeWait)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
StartupAddr: .word ASM_PFX(CEntryPoint)\r
-SecVectorTableAddr: .word ASM_PFX(SecVectorTable)\r
\r
ASM_PFX(_ModuleEntryPoint):\r
// First ensure all interrupts are disabled\r
// Only the primary core initialize the memory (SMC)\r
beq _InitMem\r
\r
-#if (FixedPcdGet32(PcdMPCoreSupport))\r
- // ... The secondary cores wait for SCU to be enabled\r
-_WaitForEnabledScu:\r
- bl ASM_PFX(ArmIsScuEnable)\r
- tst r1, #1\r
- beq _WaitForEnabledScu\r
+_WaitInitMem:\r
+ mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r
+ bl ASM_PFX(ArmCpuSynchronizeWait)\r
+ // Now the Init Mem is initialized, we setup the secondary core stacks\r
b _SetupSecondaryCoreStack\r
-#endif\r
\r
_InitMem:\r
// Initialize Init Boot Memory\r
\r
// Get the base of the stack for the secondary cores\r
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
add r1, r1, r2\r
\r
// StackOffset = CorePos * StackSize\r