+++ /dev/null
-/** @file\r
-* Header defining the BeagleBoard constants (Base addresses, sizes, flags)\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-* SPDX-License-Identifier: BSD-2-Clause-Patent\r
-*\r
-**/\r
-\r
-#ifndef __BEAGLEBOARD_PLATFORM_H__\r
-#define __BEAGLEBOARD_PLATFORM_H__\r
-\r
-// DDR attributes\r
-#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
-\r
-// SoC registers. L3 interconnects\r
-#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000\r
-#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000\r
-#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
-\r
-// SoC registers. L4 interconnects\r
-#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000\r
-#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000\r
-#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
-\r
-\r
-#if 0\r
-/*******************************************\r
-// Platform Memory Map\r
-*******************************************/\r
-\r
-// Can be NOR, DOC, DRAM, SRAM\r
-#define ARM_EB_REMAP_BASE 0x00000000\r
-#define ARM_EB_REMAP_SZ 0x04000000\r
-\r
-// Motherboard Peripheral and On-chip peripheral\r
-#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
-#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000\r
-#define ARM_EB_BOARD_PERIPH_BASE 0x10000000\r
-//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000\r
-\r
-// SMC\r
-#define ARM_EB_SMC_BASE 0x40000000\r
-#define ARM_EB_SMC_SZ 0x20000000\r
-\r
-// NOR Flash 1\r
-#define ARM_EB_SMB_NOR_BASE 0x40000000\r
-#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */\r
-// DOC Flash\r
-#define ARM_EB_SMB_DOC_BASE 0x44000000\r
-#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */\r
-// SRAM\r
-#define ARM_EB_SMB_SRAM_BASE 0x48000000\r
-#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */\r
-// USB, Ethernet, VRAM\r
-#define ARM_EB_SMB_PERIPH_BASE 0x4E000000\r
-//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000\r
-#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */\r
-\r
-// DRAM\r
-#define ARM_EB_DRAM_BASE 0x70000000\r
-#define ARM_EB_DRAM_SZ 0x10000000\r
-\r
-// Logic Tile\r
-#define ARM_EB_LOGIC_TILE_BASE 0xC0000000\r
-#define ARM_EB_LOGIC_TILE_SZ 0x40000000\r
-\r
-/*******************************************\r
-// Motherboard peripherals\r
-*******************************************/\r
-\r
-// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r
-#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
-#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
-#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
-#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
-#define ARM_EB_SYS_CLCD (ARM_EB_BOARD_PERIPH_BASE + 0x00050)\r
-#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
-#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
-#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
-#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
-#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
-\r
-// SP810 Controller\r
-#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
-\r
-// SYSTRCL Register\r
-#define ARM_EB_SYSCTRL 0x10001000\r
-\r
-// Uart0\r
-#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
-#define PL011_CONSOLE_UART_SPEED 115200\r
-\r
-// SP804 Timer Bases\r
-#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
-#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
-#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
-#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
-\r
-// PL301 RTC\r
-#define PL031_RTC_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x17000)\r
-\r
-// Dynamic Memory Controller Base\r
-#define ARM_EB_DMC_BASE 0x10018000\r
-\r
-// Static Memory Controller Base\r
-#define ARM_EB_SMC_CTRL_BASE 0x10080000\r
-\r
-#define PL111_CLCD_BASE 0x10020000\r
-//TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption\r
-#define PL111_CLCD_VRAM_BASE 0x78000000\r
-\r
-#define ARM_EB_SYS_OSCCLK4 0x1000001C\r
-\r
-\r
-/*// System Configuration Controller register Base addresses\r
-//#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000\r
-#define ARM_EB_SYS_CFGRW0_REG 0x100E2000\r
-#define ARM_EB_SYS_CFGRW1_REG 0x100E2004\r
-#define ARM_EB_SYS_CFGRW2_REG 0x100E2008\r
-\r
-#define ARM_EB_CFGRW1_REMAP_NOR0 0\r
-#define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28)\r
-#define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29)\r
-#define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30)\r
-\r
-// PL301 Fast AXI Base Address\r
-#define ARM_EB_FAXI_BASE 0x100E9000\r
-\r
-// L2x0 Cache Controller Base Address\r
-//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/\r
-\r
-\r
-// PL031 RTC - Other settings\r
-#define PL031_PPM_ACCURACY 300000000\r
-\r
-/*******************************************\r
-// Interrupt Map\r
-*******************************************/\r
-\r
-// Timer Interrupts\r
-#define TIMER01_INTERRUPT_NUM 34\r
-#define TIMER23_INTERRUPT_NUM 35\r
-\r
-\r
-/*******************************************\r
-// EFI Memory Map in Permanent Memory (DRAM)\r
-*******************************************/\r
-\r
-// This region is allocated at the bottom of the DRAM. It will be used\r
-// for fixed address allocations such as Vector Table\r
-#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB\r
-\r
-// This region is the memory declared to PEI as permanent memory for PEI\r
-// and DXE. EFI stacks and heaps will be declared in this region.\r
-#define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000\r
-#endif\r
-\r
-typedef enum {\r
- REVISION_XM,\r
- REVISION_UNKNOWN0,\r
- REVISION_UNKNOWN1,\r
- REVISION_UNKNOWN2,\r
- REVISION_UNKNOWN3,\r
- REVISION_C4,\r
- REVISION_C123,\r
- REVISION_AB,\r
-} BEAGLEBOARD_REVISION;\r
-\r
-#endif\r
projects / mirror_edk2.git / blobdiff