-#------------------------------------------------------------------------------ \r
+#------------------------------------------------------------------------------\r
#\r
-# Copyright (c) 2008-2009 Apple Inc. All rights reserved.\r
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
#\r
-# All rights reserved. This program and the accompanying materials\r
+# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution. The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
.align 3\r
\r
.globl ASM_PFX(CEntryPoint)\r
-.globl ASM_PFX(_ModuleEntryPoint)\r
+GCC_ASM_EXPORT(_ModuleEntryPoint)\r
\r
ASM_PFX(_ModuleEntryPoint):\r
\r
mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register\r
bic r0, r0, #0x00000002 // disable L2 cache\r
mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register\r
- \r
+\r
//Enable Strict alignment checking & Instruction cache\r
mrc p15, 0, r0, c1, c0, 0\r
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */\r
orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */\r
mcr p15, 0, r0, c1, c0, 0\r
\r
+ // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r
+ mrc p15, 0, r0, c1, c0, 2\r
+ orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)\r
+ mcr p15, 0, r0, c1, c0, 2\r
+ mov r0, #0x40000000 // Set EN bit in FPEXC\r
+ mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly\r
+\r
+\r
// Set CPU vectors to start of DRAM\r
- mov r0, #0x80000000\r
+ LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r
mcr p15, 0, r0, c12, c0, 0\r
-\r
- /* before we call C code, lets setup the stack pointer */\r
+ isb // Sync changes to control registers\r
+\r
+ // Fill vector table with branchs to current pc (jmp $)\r
+ ldr r1, ShouldNeverGetHere\r
+ movs r2, #0\r
+FillVectors:\r
+ str r1, [r0, r2]\r
+ adds r2, r2, #4\r
+ cmp r2, #32\r
+ bne FillVectors\r
+\r
+ /* before we call C code, lets setup the stack pointer in internal RAM */\r
stack_pointer_setup:\r
\r
//\r
- // Set stack based on PCD values. Need to do it this way to make C code work \r
- // when it runs from FLASH. \r
- // \r
+ // Set stack based on PCD values. Need to do it this way to make C code work\r
+ // when it runs from FLASH.\r
+ //\r
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */\r
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */\r
add r4, r2, r3\r
\r
- //Enter IRQ mode and set up IRQ stack pointer\r
- mov r0,#0x12|0x80|0x40\r
- msr CPSR_c,r0\r
- mov r13,r4\r
-\r
- //Enter Abort mode and set up Abort stack pointer\r
- mov r0,#0x17|0x80|0x40\r
- msr CPSR_c,r0\r
- sub r4, r4, #0x400\r
- mov r13,r4\r
-\r
- //Enter Undefined mode and set up Undefined stack pointer\r
- mov r0,#0x1b|0x80|0x40\r
- msr CPSR_c,r0\r
- sub r4, r4, #0x400\r
- mov r13,r4\r
-\r
//Enter SVC mode and set up SVC stack pointer\r
mov r0,#0x13|0x80|0x40\r
msr CPSR_c,r0\r
- sub r4, r4, #0x400\r
- mov r13,r4\r
-\r
- //Enter System mode and set up System stack pointer\r
- mov r0,#0x1f|0x80|0x40\r
- msr CPSR_c,r0\r
- sub r4, r4, #0x400\r
mov r13,r4\r
\r
// Call C entry point\r
- mov r0, #0x80000000 /* memory base arg0 */\r
- mov r1, #0x10000000 /* memory size arg1 */\r
-\r
- bl ASM_PFX(CEntryPoint) /* Assume C code is ARM */\r
+ LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) /* memory size arg1 */\r
+ LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) /* memory size arg0 */\r
+ blx ASM_PFX(CEntryPoint) /* Assume C code is thumb */\r
\r
ShouldNeverGetHere:\r
/* _CEntryPoint should never return */\r
b ShouldNeverGetHere\r
\r
- \r