Initialize DuetPkg ...

[mirror_edk2.git] / DuetPkg / DxeIpl / Ia32 / VirtualMemory.h

diff --git a/DuetPkg/DxeIpl/Ia32/VirtualMemory.h b/DuetPkg/DxeIpl/Ia32/VirtualMemory.h
new file mode 100644 (file)
index 0000000..04eab8f
--- /dev/null
+++ b/DuetPkg/DxeIpl/Ia32/VirtualMemory.h
@@ -0,0 +1,88 @@
+/*++\r
+\r
+Copyright (c) 2006, Intel Corporation                                                         \r
+All rights reserved. This program and the accompanying materials                          \r
+are licensed and made available under the terms and conditions of the BSD License         \r
+which accompanies this distribution.  The full text of the license may be found at        \r
+http://opensource.org/licenses/bsd-license.php                                            \r
+                                                                                          \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+\r
+Module Name:\r
+  VirtualMemory.h\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+\r
+--*/\r
+  \r
+#ifndef _VIRTUAL_MEMORY_H_\r
+#define _VIRTUAL_MEMORY_H_\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// Page Directory Entry 4K\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT32  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
+    UINT32  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
+    UINT32  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
+    UINT32  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT32  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
+    UINT32  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT32  MustBeZero:3;             // Must Be Zero\r
+    UINT32  Available:3;              // Available for use by system software\r
+    UINT32  PageTableBaseAddress:20;  // Page Table Base Address\r
+  } Bits;\r
+  UINT32    Uint32;\r
+} IA32_PAGE_DIRECTORY_ENTRY_4K;\r
+\r
+//\r
+// Page Table Entry 4K\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT32  Present:1;                // 0 = Not present in memory, 1 = Present in memory \r
+    UINT32  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
+    UINT32  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
+    UINT32  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT32  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
+    UINT32  Accessed:1;               // 0 = Not accessed (cleared by software), 1 = Accessed (set by CPU)\r
+    UINT32  Dirty:1;                  // 0 = Not written to (cleared by software), 1 = Written to (set by CPU)\r
+    UINT32  PAT:1;                    // 0 = Disable PAT, 1 = Enable PAT\r
+    UINT32  Global:1;                 // Ignored\r
+    UINT32  Available:3;              // Available for use by system software\r
+    UINT32  PageTableBaseAddress:20;  // Page Table Base Address\r
+  } Bits;\r
+  UINT32    Uint32;\r
+} IA32_PAGE_TABLE_ENTRY_4K;\r
+\r
+//\r
+// Page Table Entry 4M\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT32  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
+    UINT32  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
+    UINT32  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
+    UINT32  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT32  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
+    UINT32  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT32  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
+    UINT32  MustBe1:1;                // Must be 1 \r
+    UINT32  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+    UINT32  Available:3;              // Available for use by system software\r
+    UINT32  PAT:1;                    //\r
+    UINT32  MustBeZero:9;             // Must be zero;\r
+    UINT32  PageTableBaseAddress:10;  // Page Table Base Address\r
+  } Bits;\r
+  UINT32    Uint32;\r
+} IA32_PAGE_TABLE_ENTRY_4M;\r
+\r
+#pragma pack()\r
+\r
+#endif \r