1. used PciPlatfromProtocolGuid to get VgaIo and IsaIo supported capability.

[mirror_edk2.git] / IntelFrameworkModulePkg / Bus / Pci / PciBusDxe / PciCommand.h

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
index 624ec50b17ecdbeb2f50b8f82ba509c9fbf651a2..73c8c2cb77dbf9e1a4abca61f5362f8565bdd247 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
@@ -1,6 +1,6 @@
-/**@file\r
+/** @file\r
 \r
-Copyright (c) 2006, Intel Corporation                                                         \r
+Copyright (c) 2006 - 2009, Intel Corporation                                                         \r
 All rights reserved. This program and the accompanying materials                          \r
 are licensed and made available under the terms and conditions of the BSD License         \r
 which accompanies this distribution.  The full text of the license may be found at        \r
@@ -12,8 +12,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/\r
 \r
 \r
-#ifndef _EFI_PCI_COMMAND_H\r
-#define _EFI_PCI_COMMAND_H\r
+#ifndef _EFI_PCI_COMMAND_H_\r
+#define _EFI_PCI_COMMAND_H_\r
 \r
 //\r
 // The PCI Command register bits owned by PCI Bus driver.\r
@@ -87,7 +87,7 @@ PciOperateRegister (
   @param PciIoDevice  Pointer to instance of PCI_IO_DEVICE\r
   \r
   @retval TRUE  Support\r
-  @retval FALSE Not support\r
+  @retval FALSE Not support.\r
 **/\r
 BOOLEAN\r
 PciCapabilitySupport (\r
@@ -114,29 +114,100 @@ LocateCapabilityRegBlock (
   OUT UINT8         *NextRegBlock OPTIONAL\r
   );\r
 \r
+/**  \r
+  Macro that reads command register.\r
 \r
-#define PciReadCommandRegister(a,b) \\r
-        PciOperateRegister (a,0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r
-\r
-#define PciSetCommandRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r
-        \r
-#define PciEnableCommandRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
-        \r
-#define PciDisableCommandRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
-\r
-#define PciReadBridgeControlRegister(a,b) \\r
-        PciOperateRegister (a,0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r
-        \r
-#define PciSetBridgeControlRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r
-\r
-#define PciEnableBridgeControlRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
-        \r
-#define PciDisableBridgeControlRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[out]           Pointer to the 16-bit value read from command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/\r
+#define PCI_READ_COMMAND_REGISTER(a,b) \\r
+        PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r
+\r
+/**  \r
+  Macro that writes command register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The 16-bit value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/\r
+#define PCI_SET_COMMAND_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r
+\r
+/**  \r
+  Macro that enables command register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The enabled value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/        \r
+#define PCI_ENABLE_COMMAND_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
+\r
+/**  \r
+  Macro that disalbes command register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The disabled value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/        \r
+#define PCI_DISABLE_COMMAND_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
+\r
+/**  \r
+  Macro that reads PCI bridge control register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[out]           The 16-bit value read from control register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/\r
+#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \\r
+        PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r
+\r
+/**  \r
+  Macro that writes PCI bridge control register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The 16-bit value written into control register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/        \r
+#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r
+\r
+/**  \r
+  Macro that enables PCI bridge control register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The enabled value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/\r
+#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
+\r
+/**  \r
+ Macro that disalbes PCI bridge control register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The disabled value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/        \r
+#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
 \r
 #endif\r