1. used PciPlatfromProtocolGuid to get VgaIo and IsaIo supported capability.

2. Fixed ECC issues.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8591 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index 101bce18d5eceeaa26b8d688e490abbd05df7375..6808cfd53c14ff6d7f0a4ffb57fe10af6145fd43 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -100,11 +100,9 @@
   gEfiLoadFile2ProtocolGuid                                                      # SOMETIMES_CONSUMED\r
 \r
 [FeaturePcd.common]\r
-  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciVgaEnable\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport\r
-  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIsaEnable\r
 \r
-[FixedPcd.common]\r
+[Pcd.common]\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask\r
 \r
 \r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
index c69f05b53dc749544327c6d6fabab5df4b897e8a..73c8c2cb77dbf9e1a4abca61f5362f8565bdd247 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.h
@@ -1,6 +1,6 @@
 /** @file\r
 \r
-Copyright (c) 2006, Intel Corporation                                                         \r
+Copyright (c) 2006 - 2009, Intel Corporation                                                         \r
 All rights reserved. This program and the accompanying materials                          \r
 are licensed and made available under the terms and conditions of the BSD License         \r
 which accompanies this distribution.  The full text of the license may be found at        \r
@@ -114,29 +114,100 @@ LocateCapabilityRegBlock (
   OUT UINT8         *NextRegBlock OPTIONAL\r
   );\r
 \r
+/**  \r
+  Macro that reads command register.\r
 \r
-#define PciReadCommandRegister(a,b) \\r
-        PciOperateRegister (a,0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r
-\r
-#define PciSetCommandRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r
-        \r
-#define PciEnableCommandRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
-        \r
-#define PciDisableCommandRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
-\r
-#define PciReadBridgeControlRegister(a,b) \\r
-        PciOperateRegister (a,0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r
-        \r
-#define PciSetBridgeControlRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r
-\r
-#define PciEnableBridgeControlRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
-        \r
-#define PciDisableBridgeControlRegister(a,b) \\r
-        PciOperateRegister (a,b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[out]           Pointer to the 16-bit value read from command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/\r
+#define PCI_READ_COMMAND_REGISTER(a,b) \\r
+        PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r
+\r
+/**  \r
+  Macro that writes command register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The 16-bit value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/\r
+#define PCI_SET_COMMAND_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r
+\r
+/**  \r
+  Macro that enables command register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The enabled value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/        \r
+#define PCI_ENABLE_COMMAND_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
+\r
+/**  \r
+  Macro that disalbes command register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The disabled value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/        \r
+#define PCI_DISABLE_COMMAND_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
+\r
+/**  \r
+  Macro that reads PCI bridge control register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[out]           The 16-bit value read from control register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/\r
+#define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \\r
+        PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r
+\r
+/**  \r
+  Macro that writes PCI bridge control register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The 16-bit value written into control register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/        \r
+#define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r
+\r
+/**  \r
+  Macro that enables PCI bridge control register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The enabled value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/\r
+#define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r
+\r
+/**  \r
+ Macro that disalbes PCI bridge control register.\r
+\r
+  @param a[in]            Pointer to instance of PCI_IO_DEVICE.\r
+  @param b[in]            The disabled value written into command register.\r
+  \r
+  @return status of PciIo operation\r
+\r
+**/        \r
+#define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \\r
+        PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r
 \r
 #endif\r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index a75460fa974b1f4aa4b9c0d85ee2d565647d70db..08c785a23be8893ed11b18e0e308a7ac66889dc6 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -355,7 +355,7 @@ GatherDeviceInfo (
   //\r
   if (gFullEnumeration) {\r
 \r
-    PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
+    PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
 \r
   }\r
 \r
@@ -418,12 +418,12 @@ GatherPpbInfo (
     );\r
 \r
   if (gFullEnumeration) {\r
-    PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
+    PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
 \r
     //\r
     // Initalize the bridge control register\r
     //\r
-    PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);\r
+    PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);\r
 \r
   }\r
 \r
@@ -537,12 +537,12 @@ GatherP2CInfo (
     );\r
 \r
   if (gFullEnumeration) {\r
-    PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
+    PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);\r
 \r
     //\r
     // Initalize the bridge control register\r
     //\r
-    PciDisableBridgeControlRegister (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);\r
+    PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);\r
 \r
   }\r
   //\r
@@ -684,20 +684,20 @@ PciTestSupportedAttribute (
   //\r
   // Preserve the original value\r
   //\r
-  PciReadCommandRegister (PciIoDevice, OldCommand);\r
+  PCI_READ_COMMAND_REGISTER (PciIoDevice, OldCommand);\r
 \r
   //\r
   // Raise TPL to high level to disable timer interrupt while the BAR is probed\r
   //\r
   OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
 \r
-  PciSetCommandRegister (PciIoDevice, *Command);\r
-  PciReadCommandRegister (PciIoDevice, Command);\r
+  PCI_SET_COMMAND_REGISTER (PciIoDevice, *Command);\r
+  PCI_READ_COMMAND_REGISTER (PciIoDevice, Command);\r
 \r
   //\r
   // Write back the original value\r
   //\r
-  PciSetCommandRegister (PciIoDevice, *OldCommand);\r
+  PCI_SET_COMMAND_REGISTER (PciIoDevice, *OldCommand);\r
 \r
   //\r
   // Restore TPL to its original level\r
@@ -709,20 +709,20 @@ PciTestSupportedAttribute (
     //\r
     // Preserve the original value\r
     //\r
-    PciReadBridgeControlRegister (PciIoDevice, OldBridgeControl);\r
+    PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice, OldBridgeControl);\r
 \r
     //\r
     // Raise TPL to high level to disable timer interrupt while the BAR is probed\r
     //\r
     OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
 \r
-    PciSetBridgeControlRegister (PciIoDevice, *BridgeControl);\r
-    PciReadBridgeControlRegister (PciIoDevice, BridgeControl);\r
+    PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice, *BridgeControl);\r
+    PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r
 \r
     //\r
     // Write back the original value\r
     //\r
-    PciSetBridgeControlRegister (PciIoDevice, *OldBridgeControl);\r
+    PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice, *OldBridgeControl);\r
 \r
     //\r
     // Restore TPL to its original level\r
@@ -981,7 +981,7 @@ DetermineDeviceAttribute (
     //\r
     // Enable other supported attributes but not defined in PCI_IO_PROTOCOL\r
     //\r
-    PciEnableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);\r
+    PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE);\r
 \r
     //\r
     // Enable IDE native mode\r
@@ -1057,9 +1057,9 @@ DetermineDeviceAttribute (
 \r
       if (EFI_ERROR (Status) || (!FastB2BSupport)) {\r
         FastB2BSupport = FALSE;\r
-        PciDisableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);\r
+        PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);\r
       } else {\r
-        PciEnableBridgeControlRegister (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);\r
+        PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK);\r
       }\r
     }\r
 \r
@@ -1067,9 +1067,9 @@ DetermineDeviceAttribute (
     while (CurrentLink != NULL && CurrentLink != &PciIoDevice->ChildList) {\r
       Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
       if (FastB2BSupport) {\r
-        PciEnableCommandRegister (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);\r
+        PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);\r
       } else {\r
-        PciDisableCommandRegister (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);\r
+        PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_FAST_BACK_TO_BACK);\r
       }\r
 \r
       CurrentLink = CurrentLink->ForwardLink;\r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index 79755053282a75712789c61681e8c2cb54bdb09f..f2cc373b986cf5492452704fb25eb20ec83a27a4 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.c
@@ -1230,7 +1230,7 @@ SupportPaletteSnoopAttributes (
   //\r
   if (Temp->Parent == PciIoDevice->Parent) {\r
 \r
-    PciReadCommandRegister (Temp, &VGACommand);\r
+    PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);\r
 \r
     //\r
     // If they are on the same bus, either one can\r
@@ -1266,7 +1266,7 @@ SupportPaletteSnoopAttributes (
     // GFX should be set to decode\r
     //\r
     if (Operation == EfiPciIoAttributeOperationDisable) {\r
-      PciEnableCommandRegister (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
+      PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
       Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;\r
     } else {\r
       return EFI_UNSUPPORTED;\r
@@ -1277,7 +1277,7 @@ SupportPaletteSnoopAttributes (
     // GFX should be set to snoop\r
     //\r
     if (Operation == EfiPciIoAttributeOperationEnable) {\r
-      PciDisableCommandRegister (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
+      PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
       Temp->Attributes &= (~EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);\r
     } else {\r
       return EFI_UNSUPPORTED;\r
@@ -1536,9 +1536,9 @@ PciIoAttributes (
     //\r
     // Enable relevant attributes to command register and bridge control register\r
     //\r
-    Status = PciEnableCommandRegister (PciIoDevice, Command);\r
+    Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);\r
     if (BridgeControl != 0) {\r
-      Status = PciEnableBridgeControlRegister (PciIoDevice, BridgeControl);\r
+      Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r
     }\r
 \r
     PciIoDevice->Attributes |= Attributes;\r
@@ -1557,9 +1557,9 @@ PciIoAttributes (
     //\r
     // Disable relevant attributes to command register and bridge control register\r
     //\r
-    Status = PciDisableCommandRegister (PciIoDevice, Command);\r
+    Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);\r
     if (BridgeControl != 0) {\r
-      Status = PciDisableBridgeControlRegister (PciIoDevice, BridgeControl);\r
+      Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);\r
     }\r
 \r
     PciIoDevice->Attributes &= (~Attributes);\r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
index a674cadea0088b6e54ca9b482368c6c68c309188..f81bb92e3f295e7dfc95ee2d02dc4843a80c2e10 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
@@ -595,14 +595,14 @@ RomDecode (
     //\r
     // Setting the memory space bit in the function's command register\r
     //\r
-    PciEnableCommandRegister(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);\r
+    PCI_ENABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);\r
 \r
   } else {\r
 \r
     //\r
     // disable command register decode to memory\r
     //\r
-    PciDisableCommandRegister(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);\r
+    PCI_DISABLE_COMMAND_REGISTER(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);\r
 \r
     //\r
     // Destroy the programmed bar in all the upstream bridge.\r

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
index e7e40012c3b5dd9237c7c70ec704227edd93542b..da0cfa0cae86121ce5282d044a6cf87a51dde964 100644 (file)
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
@@ -196,13 +196,15 @@ CalculateApertureIo16 (
   IN PCI_RESOURCE_NODE *Bridge\r
   )\r
 {\r
-\r
-  UINT64            Aperture;\r
-  LIST_ENTRY        *CurrentLink;\r
-  PCI_RESOURCE_NODE *Node;\r
-  UINT64            Offset;\r
-  BOOLEAN           IsaEnable;\r
-  BOOLEAN           VGAEnable;\r
+  EFI_STATUS              Status;\r
+  UINT64                  Aperture;\r
+  LIST_ENTRY              *CurrentLink;\r
+  PCI_RESOURCE_NODE       *Node;\r
+  UINT64                  Offset;\r
+  BOOLEAN                 IsaEnable;\r
+  BOOLEAN                 VGAEnable;\r
+  EFI_PCI_PLATFORM_POLICY PciPolicy;\r
+  \r
 \r
   //\r
   // Always assume there is ISA device and VGA device on the platform\r
@@ -211,12 +213,22 @@ CalculateApertureIo16 (
   IsaEnable = FALSE;\r
   VGAEnable = FALSE;\r
 \r
-  if (FeaturePcdGet (PcdPciIsaEnable)){\r
-    IsaEnable = TRUE;\r
-  }\r
-\r
-  if (FeaturePcdGet (PcdPciVgaEnable)){\r
-    VGAEnable = TRUE;\r
+  //\r
+  // Check PciPlatform policy\r
+  //\r
+  if (gPciPlatformProtocol != NULL) {\r
+    Status = gPciPlatformProtocol->GetPlatformPolicy (\r
+                                     gPciPlatformProtocol,\r
+                                     &PciPolicy\r
+                                     );\r
+    if (!EFI_ERROR (Status)) {\r
+      if (PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) {\r
+        IsaEnable = TRUE;\r
+      }\r
+      if (PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) {\r
+        VGAEnable = TRUE;\r
+      }\r
+    }\r
   }\r
 \r
   Aperture = 0;\r
@@ -1386,10 +1398,10 @@ ProgrameUpstreamBridgeForRom (
     //\r
     if (Enable) {\r
       ProgramPpbApperture (OptionRomBase, &Node);\r
-      PciEnableCommandRegister (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
+      PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
     } else {\r
       InitializePpb (Parent);\r
-      PciDisableCommandRegister (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
+      PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
     }\r
 \r
     Parent = Parent->Parent;\r