-/**@file\r
+/** @file\r
+ Internal library implementation for PCI Bus module.\r
\r
- PCI Bus Driver Lib file\r
- It abstracts some functions that can be different\r
- between light PCI bus driver and full PCI bus driver\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
\r
-Copyright (c) 2006, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
-#include "pcibus.h"\r
+#include "PciBus.h"\r
\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL gPciHotPlugRequest = {\r
- PciHotPlugRequestNotify\r
-};\r
\r
+/**\r
+ Retrieve the PCI Card device BAR information via PciIo interface.\r
\r
-VOID\r
-InstallHotPlugRequestProtocol (\r
- IN EFI_STATUS *Status\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
- Status - A pointer to the status.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_HANDLE Handle;\r
-\r
- if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return;\r
- }\r
-\r
- Handle = NULL;\r
- *Status = gBS->InstallProtocolInterface (\r
- &Handle,\r
- &gEfiPciHotPlugRequestProtocolGuid,\r
- EFI_NATIVE_INTERFACE,\r
- &gPciHotPlugRequest\r
- );\r
-}\r
-\r
-VOID\r
-InstallPciHotplugGuid (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
- PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
-\r
- if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return;\r
- }\r
-\r
- if (IS_CARDBUS_BRIDGE (&PciIoDevice->Parent->Pci)) {\r
-\r
- Status = gBS->InstallProtocolInterface (\r
- &PciIoDevice->Handle,\r
- &gEfiPciHotplugDeviceGuid,\r
- EFI_NATIVE_INTERFACE,\r
- NULL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
-}\r
-\r
-VOID\r
-UninstallPciHotplugGuid (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
- PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-{\r
- EFI_STATUS Status;\r
-\r
- if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return;\r
- }\r
-\r
- Status = gBS->OpenProtocol (\r
- PciIoDevice->Handle,\r
- &gEfiPciHotplugDeviceGuid,\r
- NULL,\r
- NULL,\r
- NULL,\r
- EFI_OPEN_PROTOCOL_TEST_PROTOCOL\r
- );\r
-\r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // This may triger CardBus driver to stop for\r
- // Pccard devices opened the GUID via BY_DRIVER\r
- //\r
- Status = gBS->UninstallProtocolInterface (\r
- PciIoDevice->Handle,\r
- &gEfiPciHotplugDeviceGuid,\r
- NULL\r
- );\r
- }\r
-}\r
+ @param PciIoDevice PCI Card device instance.\r
\r
+**/\r
VOID\r
GetBackPcCardBar (\r
IN PCI_IO_DEVICE *PciIoDevice\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
-\r
-Arguments:\r
-\r
- PciIoDevice - A pointer to the PCI_IO_DEVICE.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
{\r
UINT32 Address;\r
\r
// Read PciBar information from the bar register\r
//\r
if (!gFullEnumeration) {\r
-\r
Address = 0;\r
PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- 0x1c,\r
- 1,\r
- &Address\r
- );\r
+ &(PciIoDevice->PciIo),\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_0,\r
+ 1,\r
+ &Address\r
+ );\r
\r
(PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64) (Address);\r
(PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000;\r
\r
Address = 0;\r
PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- 0x20,\r
- 1,\r
- &Address\r
- );\r
+ &(PciIoDevice->PciIo),\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_1,\r
+ 1,\r
+ &Address\r
+ );\r
(PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64) (Address);\r
(PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000;\r
(PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;\r
\r
Address = 0;\r
PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- 0x2c,\r
- 1,\r
- &Address\r
- );\r
+ &(PciIoDevice->PciIo),\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_0_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
(PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64) (Address);\r
(PciIoDevice->PciBar)[P2C_IO_1].Length = 0x100;\r
(PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16;\r
\r
Address = 0;\r
PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- 0x34,\r
- 1,\r
- &Address\r
- );\r
+ &(PciIoDevice->PciIo),\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_1_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
(PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64) (Address);\r
(PciIoDevice->PciBar)[P2C_IO_2].Length = 0x100;\r
(PciIoDevice->PciBar)[P2C_IO_2].BarType = PciBarTypeIo16;\r
\r
}\r
\r
- if (gPciHotPlugInit != NULL) {\r
+ if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
GetResourcePaddingForHpb (PciIoDevice);\r
}\r
}\r
\r
-EFI_STATUS\r
-RemoveRejectedPciDevices (\r
- EFI_HANDLE RootBridgeHandle,\r
- IN PCI_IO_DEVICE *Bridge\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-\r
-Arguments:\r
-\r
- RootBridgeHandle - An efi handle.\r
- Bridge - An pointer to the PCI_IO_DEVICE.\r
-\r
-Returns:\r
+/**\r
+ Remove rejected pci device from specific root bridge\r
+ handle.\r
\r
- None\r
+ @param RootBridgeHandle Specific parent root bridge handle.\r
+ @param Bridge Bridge device instance.\r
\r
---*/\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+RemoveRejectedPciDevices (\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN PCI_IO_DEVICE *Bridge\r
+ )\r
{\r
PCI_IO_DEVICE *Temp;\r
LIST_ENTRY *CurrentLink;\r
LIST_ENTRY *LastLink;\r
\r
if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return EFI_SUCCESS;\r
+ return;\r
}\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
\r
- while (CurrentLink && CurrentLink != &Bridge->ChildList) {\r
+ while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
\r
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
\r
//\r
// For P2C, remove all devices on it\r
//\r
-\r
if (!IsListEmpty (&Temp->ChildList)) {\r
RemoveAllPciDeviceOnBridge (RootBridgeHandle, Temp);\r
}\r
//\r
// Finally remove itself\r
//\r
-\r
LastLink = CurrentLink->BackLink;\r
RemoveEntryList (CurrentLink);\r
FreePciDevice (Temp);\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-PciHostBridgeResourceAllocator (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-{\r
- if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (\r
- PciResAlloc\r
- );\r
- } else {\r
- return PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (\r
- PciResAlloc\r
- );\r
- }\r
-}\r
+/**\r
+ Submits the I/O and memory resource requirements for the specified PCI Host Bridge.\r
\r
+ @param PciResAlloc Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
\r
+ @retval EFI_SUCCESS Successfully finished resource allocation.\r
+ @retval EFI_NOT_FOUND Cannot get root bridge instance.\r
+ @retval EFI_OUT_OF_RESOURCES Platform failed to program the resources if no hot plug supported.\r
+ @retval other Some error occurred when allocating resources for the PCI Host Bridge.\r
+\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
+\r
+**/\r
EFI_STATUS\r
-PciHostBridgeResourceAllocator_WithoutHotPlugDeviceSupport (\r
+PciHostBridgeResourceAllocator (\r
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: PciResAlloc - add argument and description to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
- PCI_IO_DEVICE *RootBridgeDev;\r
- EFI_HANDLE RootBridgeHandle;\r
- VOID *AcpiConfig;\r
- EFI_STATUS Status;\r
- UINT64 IoBase;\r
- UINT64 Mem32Base;\r
- UINT64 PMem32Base;\r
- UINT64 Mem64Base;\r
- UINT64 PMem64Base;\r
- UINT64 MaxOptionRomSize;\r
- PCI_RESOURCE_NODE *IoBridge;\r
- PCI_RESOURCE_NODE *Mem32Bridge;\r
- PCI_RESOURCE_NODE *PMem32Bridge;\r
- PCI_RESOURCE_NODE *Mem64Bridge;\r
- PCI_RESOURCE_NODE *PMem64Bridge;\r
- PCI_RESOURCE_NODE IoPool;\r
- PCI_RESOURCE_NODE Mem32Pool;\r
- PCI_RESOURCE_NODE PMem32Pool;\r
- PCI_RESOURCE_NODE Mem64Pool;\r
- PCI_RESOURCE_NODE PMem64Pool;\r
- EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD ExtendedData;\r
+ PCI_IO_DEVICE *RootBridgeDev;\r
+ EFI_HANDLE RootBridgeHandle;\r
+ VOID *AcpiConfig;\r
+ EFI_STATUS Status;\r
+ UINT64 IoBase;\r
+ UINT64 Mem32Base;\r
+ UINT64 PMem32Base;\r
+ UINT64 Mem64Base;\r
+ UINT64 PMem64Base;\r
+ UINT64 IoResStatus;\r
+ UINT64 Mem32ResStatus;\r
+ UINT64 PMem32ResStatus;\r
+ UINT64 Mem64ResStatus;\r
+ UINT64 PMem64ResStatus;\r
+ UINT64 MaxOptionRomSize;\r
+ PCI_RESOURCE_NODE *IoBridge;\r
+ PCI_RESOURCE_NODE *Mem32Bridge;\r
+ PCI_RESOURCE_NODE *PMem32Bridge;\r
+ PCI_RESOURCE_NODE *Mem64Bridge;\r
+ PCI_RESOURCE_NODE *PMem64Bridge;\r
+ PCI_RESOURCE_NODE IoPool;\r
+ PCI_RESOURCE_NODE Mem32Pool;\r
+ PCI_RESOURCE_NODE PMem32Pool;\r
+ PCI_RESOURCE_NODE Mem64Pool;\r
+ PCI_RESOURCE_NODE PMem64Pool;\r
+ BOOLEAN ReAllocate;\r
+ EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;\r
+ EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
\r
//\r
- // Initialize resource pool\r
+ // Reallocate flag\r
//\r
+ ReAllocate = FALSE;\r
\r
- InitializeResourcePool (&IoPool, PciBarTypeIo16);\r
- InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);\r
- InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);\r
- InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);\r
- InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);\r
-\r
- RootBridgeDev = NULL;\r
- RootBridgeHandle = 0;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
+ //\r
+ // It may try several times if the resource allocation fails\r
+ //\r
+ while (TRUE) {\r
//\r
- // Get host bridge handle for status report\r
+ // Initialize resource pool\r
//\r
- ExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
+ InitializeResourcePool (&IoPool, PciBarTypeIo16);\r
+ InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);\r
+ InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);\r
+ InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);\r
+ InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);\r
\r
- //\r
- // Create the entire system resource map from the information collected by\r
- // enumerator. Several resource tree was created\r
- //\r
+ RootBridgeDev = NULL;\r
+ RootBridgeHandle = 0;\r
\r
- IoBridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFF,\r
- 0,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- );\r
+ while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
+ //\r
+ // Get Root Bridge Device by handle\r
+ //\r
+ RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
\r
- Mem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem32,\r
- PciResUsageTypical\r
- );\r
+ if (RootBridgeDev == NULL) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
\r
- PMem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
+ //\r
+ // Create the entire system resource map from the information collected by\r
+ // enumerator. Several resource tree was created\r
+ //\r
\r
- Mem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem64,\r
- PciResUsageTypical\r
- );\r
+ IoBridge = CreateResourceNode (\r
+ RootBridgeDev,\r
+ 0,\r
+ 0xFFF,\r
+ 0,\r
+ PciBarTypeIo16,\r
+ PciResUsageTypical\r
+ );\r
\r
- PMem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
+ Mem32Bridge = CreateResourceNode (\r
+ RootBridgeDev,\r
+ 0,\r
+ 0xFFFFF,\r
+ 0,\r
+ PciBarTypeMem32,\r
+ PciResUsageTypical\r
+ );\r
\r
- //\r
- // Create resourcemap by going through all the devices subject to this root bridge\r
- //\r
- Status = CreateResourceMap (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge\r
- );\r
+ PMem32Bridge = CreateResourceNode (\r
+ RootBridgeDev,\r
+ 0,\r
+ 0xFFFFF,\r
+ 0,\r
+ PciBarTypePMem32,\r
+ PciResUsageTypical\r
+ );\r
\r
- //\r
- // Get the max ROM size that the root bridge can process\r
- //\r
- RootBridgeDev->RomSize = Mem32Bridge->Length;\r
+ Mem64Bridge = CreateResourceNode (\r
+ RootBridgeDev,\r
+ 0,\r
+ 0xFFFFF,\r
+ 0,\r
+ PciBarTypeMem64,\r
+ PciResUsageTypical\r
+ );\r
\r
- //\r
- // Get Max Option Rom size for current root bridge\r
- //\r
- MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
+ PMem64Bridge = CreateResourceNode (\r
+ RootBridgeDev,\r
+ 0,\r
+ 0xFFFFF,\r
+ 0,\r
+ PciBarTypePMem64,\r
+ PciResUsageTypical\r
+ );\r
\r
- //\r
- // Enlarger the mem32 resource to accomdate the option rom\r
- // if the mem32 resource is not enough to hold the rom\r
- //\r
- if (MaxOptionRomSize > Mem32Bridge->Length) {\r
+ //\r
+ // Create resourcemap by going through all the devices subject to this root bridge\r
+ //\r
+ CreateResourceMap (\r
+ RootBridgeDev,\r
+ IoBridge,\r
+ Mem32Bridge,\r
+ PMem32Bridge,\r
+ Mem64Bridge,\r
+ PMem64Bridge\r
+ );\r
\r
- Mem32Bridge->Length = MaxOptionRomSize;\r
- RootBridgeDev->RomSize = MaxOptionRomSize;\r
+ //\r
+ // Get the max ROM size that the root bridge can process\r
+ //\r
+ RootBridgeDev->RomSize = Mem32Bridge->Length;\r
\r
//\r
- // Alignment should be adjusted as well\r
+ // Skip to enlarge the resource request during realloction\r
//\r
- if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {\r
- Mem32Bridge->Alignment = MaxOptionRomSize - 1;\r
- }\r
- }\r
+ if (!ReAllocate) {\r
+ //\r
+ // Get Max Option Rom size for current root bridge\r
+ //\r
+ MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
\r
- //\r
- // Based on the all the resource tree, contruct ACPI resource node to\r
- // submit the resource aperture to pci host bridge protocol\r
- //\r
- Status = ConstructAcpiResourceRequestor (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge,\r
- &AcpiConfig\r
- );\r
+ //\r
+ // Enlarger the mem32 resource to accomdate the option rom\r
+ // if the mem32 resource is not enough to hold the rom\r
+ //\r
+ if (MaxOptionRomSize > Mem32Bridge->Length) {\r
\r
- //\r
- // Insert these resource nodes into the database\r
- //\r
- InsertResourceNode (&IoPool, IoBridge);\r
- InsertResourceNode (&Mem32Pool, Mem32Bridge);\r
- InsertResourceNode (&PMem32Pool, PMem32Bridge);\r
- InsertResourceNode (&Mem64Pool, Mem64Bridge);\r
- InsertResourceNode (&PMem64Pool, PMem64Bridge);\r
+ Mem32Bridge->Length = MaxOptionRomSize;\r
+ RootBridgeDev->RomSize = MaxOptionRomSize;\r
+\r
+ //\r
+ // Alignment should be adjusted as well\r
+ //\r
+ if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {\r
+ Mem32Bridge->Alignment = MaxOptionRomSize - 1;\r
+ }\r
+ }\r
+ }\r
\r
- if (Status == EFI_SUCCESS) {\r
//\r
- // Submit the resource requirement\r
+ // Based on the all the resource tree, contruct ACPI resource node to\r
+ // submit the resource aperture to pci host bridge protocol\r
//\r
- Status = PciResAlloc->SubmitResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- AcpiConfig\r
- );\r
- }\r
- //\r
- // Free acpi resource node\r
- //\r
- if (AcpiConfig != NULL) {\r
- FreePool (AcpiConfig);\r
- }\r
+ Status = ConstructAcpiResourceRequestor (\r
+ RootBridgeDev,\r
+ IoBridge,\r
+ Mem32Bridge,\r
+ PMem32Bridge,\r
+ Mem64Bridge,\r
+ PMem64Bridge,\r
+ &AcpiConfig\r
+ );\r
\r
- if (EFI_ERROR (Status)) {\r
//\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
- return Status;\r
- }\r
- }\r
- //\r
- // End while\r
- //\r
-\r
- //\r
- // Notify pci bus driver starts to program the resource\r
- //\r
- Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);\r
-\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // Allocation failed, then return\r
- //\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
- //\r
- // Raise the EFI_IOB_PCI_RES_ALLOC status code\r
- //\r
- REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
- EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_PCI_PC_RES_ALLOC,\r
- (VOID *) &ExtendedData,\r
- sizeof (ExtendedData)\r
- );\r
-\r
- //\r
- // Notify pci bus driver starts to program the resource\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);\r
-\r
- RootBridgeDev = NULL;\r
-\r
- RootBridgeHandle = 0;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Get acpi resource node for all the resource types\r
- //\r
- AcpiConfig = NULL;\r
- Status = PciResAlloc->GetProposedResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- &AcpiConfig\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Get the resource base by interpreting acpi resource node\r
- //\r
- //\r
- GetResourceBase (\r
- AcpiConfig,\r
- &IoBase,\r
- &Mem32Base,\r
- &PMem32Base,\r
- &Mem64Base,\r
- &PMem64Base\r
- );\r
-\r
- //\r
- // Process option rom for this root bridge\r
- //\r
- Status = ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
-\r
- //\r
- // Create the entire system resource map from the information collected by\r
- // enumerator. Several resource tree was created\r
- //\r
- Status = GetResourceMap (\r
- RootBridgeDev,\r
- &IoBridge,\r
- &Mem32Bridge,\r
- &PMem32Bridge,\r
- &Mem64Bridge,\r
- &PMem64Bridge,\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Program IO resources\r
- //\r
- ProgramResource (\r
- IoBase,\r
- IoBridge\r
- );\r
-\r
- //\r
- // Program Mem32 resources\r
- //\r
- ProgramResource (\r
- Mem32Base,\r
- Mem32Bridge\r
- );\r
-\r
- //\r
- // Program PMem32 resources\r
- //\r
- ProgramResource (\r
- PMem32Base,\r
- PMem32Bridge\r
- );\r
-\r
- //\r
- // Program Mem64 resources\r
- //\r
- ProgramResource (\r
- Mem64Base,\r
- Mem64Bridge\r
- );\r
-\r
- //\r
- // Program PMem64 resources\r
- //\r
- ProgramResource (\r
- PMem64Base,\r
- PMem64Bridge\r
- );\r
-\r
- if (AcpiConfig != NULL) {\r
- FreePool (AcpiConfig);\r
- }\r
- }\r
-\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
-\r
- //\r
- // Notify the resource allocation phase is to end\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciHostBridgeResourceAllocator_WithHotPlugDeviceSupport (\r
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Host brige resource allocator.\r
-\r
-Arguments:\r
-\r
- PciResAlloc - A pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
-\r
-Returns:\r
-\r
- EFI Status.\r
-\r
---*/\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- PCI_IO_DEVICE *RootBridgeDev;\r
- EFI_HANDLE RootBridgeHandle;\r
- VOID *AcpiConfig;\r
- EFI_STATUS Status;\r
- UINT64 IoBase;\r
- UINT64 Mem32Base;\r
- UINT64 PMem32Base;\r
- UINT64 Mem64Base;\r
- UINT64 PMem64Base;\r
- UINT64 IoResStatus;\r
- UINT64 Mem32ResStatus;\r
- UINT64 PMem32ResStatus;\r
- UINT64 Mem64ResStatus;\r
- UINT64 PMem64ResStatus;\r
- UINT64 MaxOptionRomSize;\r
- PCI_RESOURCE_NODE *IoBridge;\r
- PCI_RESOURCE_NODE *Mem32Bridge;\r
- PCI_RESOURCE_NODE *PMem32Bridge;\r
- PCI_RESOURCE_NODE *Mem64Bridge;\r
- PCI_RESOURCE_NODE *PMem64Bridge;\r
- PCI_RESOURCE_NODE IoPool;\r
- PCI_RESOURCE_NODE Mem32Pool;\r
- PCI_RESOURCE_NODE PMem32Pool;\r
- PCI_RESOURCE_NODE Mem64Pool;\r
- PCI_RESOURCE_NODE PMem64Pool;\r
- BOOLEAN ReAllocate;\r
- EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;\r
- EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;\r
-\r
- //\r
- // Reallocate flag\r
- //\r
- ReAllocate = FALSE;\r
-\r
- //\r
- // It will try several times if the resource allocation fails\r
- //\r
- while (TRUE) {\r
-\r
- //\r
- // Initialize resource pool\r
- //\r
- InitializeResourcePool (&IoPool, PciBarTypeIo16);\r
- InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);\r
- InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);\r
- InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);\r
- InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);\r
-\r
- RootBridgeDev = NULL;\r
- RootBridgeHandle = 0;\r
-\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
- //\r
- // Get RootBridg Device by handle\r
- //\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
-\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- //\r
- // Create the entire system resource map from the information collected by\r
- // enumerator. Several resource tree was created\r
- //\r
-\r
- IoBridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFF,\r
- 0,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- );\r
-\r
- Mem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem32,\r
- PciResUsageTypical\r
- );\r
-\r
- PMem32Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
-\r
- Mem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypeMem64,\r
- PciResUsageTypical\r
- );\r
-\r
- PMem64Bridge = CreateResourceNode (\r
- RootBridgeDev,\r
- 0,\r
- 0xFFFFF,\r
- 0,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
-\r
- //\r
- // Create resourcemap by going through all the devices subject to this root bridge\r
- //\r
- Status = CreateResourceMap (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge\r
- );\r
-\r
- //\r
- // Get the max ROM size that the root bridge can process\r
- //\r
- RootBridgeDev->RomSize = Mem32Bridge->Length;\r
-\r
- //\r
- // Skip to enlarge the resource request during realloction\r
- //\r
- if (!ReAllocate) {\r
- //\r
- // Get Max Option Rom size for current root bridge\r
- //\r
- MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);\r
-\r
- //\r
- // Enlarger the mem32 resource to accomdate the option rom\r
- // if the mem32 resource is not enough to hold the rom\r
- //\r
- if (MaxOptionRomSize > Mem32Bridge->Length) {\r
-\r
- Mem32Bridge->Length = MaxOptionRomSize;\r
- RootBridgeDev->RomSize = MaxOptionRomSize;\r
-\r
- //\r
- // Alignment should be adjusted as well\r
- //\r
- if (Mem32Bridge->Alignment < MaxOptionRomSize - 1) {\r
- Mem32Bridge->Alignment = MaxOptionRomSize - 1;\r
- }\r
- }\r
- }\r
-\r
- //\r
- // Based on the all the resource tree, contruct ACPI resource node to\r
- // submit the resource aperture to pci host bridge protocol\r
- //\r
- Status = ConstructAcpiResourceRequestor (\r
- RootBridgeDev,\r
- IoBridge,\r
- Mem32Bridge,\r
- PMem32Bridge,\r
- Mem64Bridge,\r
- PMem64Bridge,\r
- &AcpiConfig\r
- );\r
-\r
- //\r
- // Insert these resource nodes into the database\r
+ // Insert these resource nodes into the database\r
//\r
InsertResourceNode (&IoPool, IoBridge);\r
InsertResourceNode (&Mem32Pool, Mem32Bridge);\r
return Status;\r
}\r
}\r
-\r
//\r
- // Notify pci bus driver starts to program the resource\r
+ // End while\r
//\r
\r
+ //\r
+ // Notify platform to start to program the resource\r
+ //\r
Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);\r
-\r
- if (!EFI_ERROR (Status)) {\r
+ if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
//\r
- // Allocation succeed, then continue the following\r
+ // If Hot Plug is not supported\r
//\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Allocation failed, then return\r
+ //\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+ //\r
+ // Allocation succeed.\r
+ // Get host bridge handle for status report, and then skip the main while\r
+ //\r
+ HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
+\r
break;\r
- }\r
\r
- //\r
- // If the resource allocation is unsuccessful, free resources on bridge\r
- //\r
+ } else {\r
+ //\r
+ // If Hot Plug is supported\r
+ //\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // Allocation succeed, then continue the following\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // If the resource allocation is unsuccessful, free resources on bridge\r
+ //\r
+\r
+ RootBridgeDev = NULL;\r
+ RootBridgeHandle = 0;\r
+\r
+ IoResStatus = EFI_RESOURCE_SATISFIED;\r
+ Mem32ResStatus = EFI_RESOURCE_SATISFIED;\r
+ PMem32ResStatus = EFI_RESOURCE_SATISFIED;\r
+ Mem64ResStatus = EFI_RESOURCE_SATISFIED;\r
+ PMem64ResStatus = EFI_RESOURCE_SATISFIED;\r
+\r
+ while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
+ //\r
+ // Get RootBridg Device by handle\r
+ //\r
+ RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
+ if (RootBridgeDev == NULL) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Get host bridge handle for status report\r
+ //\r
+ HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
\r
- RootBridgeDev = NULL;\r
- RootBridgeHandle = 0;\r
+ //\r
+ // Get acpi resource node for all the resource types\r
+ //\r
+ AcpiConfig = NULL;\r
\r
- IoResStatus = EFI_RESOURCE_SATISFIED;\r
- Mem32ResStatus = EFI_RESOURCE_SATISFIED;\r
- PMem32ResStatus = EFI_RESOURCE_SATISFIED;\r
- Mem64ResStatus = EFI_RESOURCE_SATISFIED;\r
- PMem64ResStatus = EFI_RESOURCE_SATISFIED;\r
+ Status = PciResAlloc->GetProposedResources (\r
+ PciResAlloc,\r
+ RootBridgeDev->Handle,\r
+ &AcpiConfig\r
+ );\r
\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if (AcpiConfig != NULL) {\r
+ //\r
+ // Adjust resource allocation policy for each RB\r
+ //\r
+ GetResourceAllocationStatus (\r
+ AcpiConfig,\r
+ &IoResStatus,\r
+ &Mem32ResStatus,\r
+ &PMem32ResStatus,\r
+ &Mem64ResStatus,\r
+ &PMem64ResStatus\r
+ );\r
+ FreePool (AcpiConfig);\r
+ }\r
+ }\r
//\r
- // Get RootBridg Device by handle\r
+ // End while\r
//\r
- RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);\r
- if (RootBridgeDev == NULL) {\r
- return EFI_NOT_FOUND;\r
- }\r
\r
//\r
- // Get host bridge handle for status report\r
+ // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
//\r
- HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;\r
+ //\r
+ // It is very difficult to follow the spec here\r
+ // Device path , Bar index can not be get here\r
+ //\r
+ ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
+\r
+ REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
+ EFI_PROGRESS_CODE,\r
+ EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
+ (VOID *) &AllocFailExtendedData,\r
+ sizeof (AllocFailExtendedData)\r
+ );\r
+\r
+ Status = PciHostBridgeAdjustAllocation (\r
+ &IoPool,\r
+ &Mem32Pool,\r
+ &PMem32Pool,\r
+ &Mem64Pool,\r
+ &PMem64Pool,\r
+ IoResStatus,\r
+ Mem32ResStatus,\r
+ PMem32ResStatus,\r
+ Mem64ResStatus,\r
+ PMem64ResStatus\r
+ );\r
\r
//\r
- // Get acpi resource node for all the resource types\r
+ // Destroy all the resource tree\r
//\r
- AcpiConfig = NULL;\r
+ DestroyResourceTree (&IoPool);\r
+ DestroyResourceTree (&Mem32Pool);\r
+ DestroyResourceTree (&PMem32Pool);\r
+ DestroyResourceTree (&Mem64Pool);\r
+ DestroyResourceTree (&PMem64Pool);\r
\r
- Status = PciResAlloc->GetProposedResources (\r
- PciResAlloc,\r
- RootBridgeDev->Handle,\r
- &AcpiConfig\r
- );\r
+ NotifyPhase (PciResAlloc, EfiPciHostBridgeFreeResources);\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- if (AcpiConfig != NULL) {\r
- //\r
- // Adjust resource allocation policy for each RB\r
- //\r
- GetResourceAllocationStatus (\r
- AcpiConfig,\r
- &IoResStatus,\r
- &Mem32ResStatus,\r
- &PMem32ResStatus,\r
- &Mem64ResStatus,\r
- &PMem64ResStatus\r
- );\r
- FreePool (AcpiConfig);\r
- }\r
- }\r
- //\r
- // End while\r
- //\r
-\r
- //\r
- // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code\r
- //\r
- //\r
- // It is very difficult to follow the spec here\r
- // Device path , Bar index can not be get here\r
- //\r
- ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));\r
-\r
- REPORT_STATUS_CODE_WITH_EXTENDED_DATA (\r
- EFI_PROGRESS_CODE,\r
- EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,\r
- (VOID *) &AllocFailExtendedData,\r
- sizeof (AllocFailExtendedData)\r
- );\r
-\r
- Status = PciHostBridgeAdjustAllocation (\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool,\r
- IoResStatus,\r
- Mem32ResStatus,\r
- PMem32ResStatus,\r
- Mem64ResStatus,\r
- PMem64ResStatus\r
- );\r
-\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
-\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeFreeResources);\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
+ ReAllocate = TRUE;\r
}\r
-\r
- ReAllocate = TRUE;\r
-\r
}\r
//\r
// End main while\r
RootBridgeHandle = 0;\r
\r
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
-\r
//\r
// Get RootBridg Device by handle\r
//\r
//\r
// Process option rom for this root bridge\r
//\r
- Status = ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
+ ProcessOptionRom (RootBridgeDev, Mem32Base, RootBridgeDev->RomSize);\r
\r
//\r
// Create the entire system resource map from the information collected by\r
// enumerator. Several resource tree was created\r
//\r
- Status = GetResourceMap (\r
- RootBridgeDev,\r
- &IoBridge,\r
- &Mem32Bridge,\r
- &PMem32Bridge,\r
- &Mem64Bridge,\r
- &PMem64Bridge,\r
- &IoPool,\r
- &Mem32Pool,\r
- &PMem32Pool,\r
- &Mem64Pool,\r
- &PMem64Pool\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ GetResourceMap (\r
+ RootBridgeDev,\r
+ &IoBridge,\r
+ &Mem32Bridge,\r
+ &PMem32Bridge,\r
+ &Mem64Bridge,\r
+ &PMem64Bridge,\r
+ &IoPool,\r
+ &Mem32Pool,\r
+ &PMem32Pool,\r
+ &Mem64Pool,\r
+ &PMem64Pool\r
+ );\r
\r
//\r
// Program IO resources\r
// Program PMem64 resources\r
//\r
ProgramResource (\r
- PMem64Base,\r
- PMem64Bridge\r
- );\r
-\r
- if (AcpiConfig != NULL) {\r
- gBS->FreePool (AcpiConfig);\r
- }\r
- }\r
-\r
- //\r
- // Destroy all the resource tree\r
- //\r
- DestroyResourceTree (&IoPool);\r
- DestroyResourceTree (&Mem32Pool);\r
- DestroyResourceTree (&PMem32Pool);\r
- DestroyResourceTree (&Mem64Pool);\r
- DestroyResourceTree (&PMem64Pool);\r
-\r
- //\r
- // Notify the resource allocation phase is to end\r
- //\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciScanBus (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber,\r
- OUT UINT8 *SubBusNumber,\r
- OUT UINT8 *PaddedBusRange\r
- )\r
-{\r
- if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
- return PciScanBus_WithHotPlugDeviceSupport (\r
- Bridge,\r
- StartBusNumber,\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
- } else {\r
- return PciScanBus_WithoutHotPlugDeviceSupport (\r
- Bridge,\r
- StartBusNumber,\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
- }\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciScanBus_WithoutHotPlugDeviceSupport (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN UINT8 StartBusNumber,\r
- OUT UINT8 *SubBusNumber,\r
- OUT UINT8 *PaddedBusRange\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is used to assign bus number to the given PCI bus system\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: StartBusNumber - add argument and description to function comment\r
-// TODO: SubBusNumber - add argument and description to function comment\r
-// TODO: PaddedBusRange - add argument and description to function comment\r
-// TODO: EFI_DEVICE_ERROR - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- EFI_STATUS Status;\r
- PCI_TYPE00 Pci;\r
- UINT8 Device;\r
- UINT8 Func;\r
- UINT64 Address;\r
- UINTN SecondBus;\r
- UINT16 Register;\r
- PCI_IO_DEVICE *PciDevice;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
-\r
- PciRootBridgeIo = Bridge->PciRootBridgeIo;\r
- SecondBus = 0;\r
- Register = 0;\r
-\r
- for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
- for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
-\r
- //\r
- // Check to see whether a pci device is present\r
- //\r
- Status = PciDevicePresent (\r
- PciRootBridgeIo,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func\r
- );\r
-\r
- if (!EFI_ERROR (Status) &&\r
- (IS_PCI_BRIDGE (&Pci) ||\r
- IS_CARDBUS_BRIDGE (&Pci))) {\r
-\r
- DEBUG((EFI_D_ERROR, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));\r
-\r
- //\r
- // Get the bridge information\r
- //\r
- Status = PciSearchDevice (\r
- Bridge,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func,\r
- &PciDevice\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Add feature to support customized secondary bus number\r
- //\r
- if (*SubBusNumber == 0) { \r
- *SubBusNumber = *PaddedBusRange;\r
- *PaddedBusRange = 0;\r
- }\r
-\r
- (*SubBusNumber)++;\r
-\r
- SecondBus = (*SubBusNumber);\r
-\r
- Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
-\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
-\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint16,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
-\r
- //\r
- // Initialize SubBusNumber to SecondBus\r
- //\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- SubBusNumber\r
- );\r
- //\r
- // If it is PPB, resursively search down this bridge\r
- //\r
- if (IS_PCI_BRIDGE (&Pci)) {\r
- //\r
- // Temporarily initialize SubBusNumber to maximum bus number to ensure the\r
- // PCI configuration transaction to go through any PPB\r
- //\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- Register = 0xFF;\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
-\r
- PreprocessController (\r
- PciDevice,\r
- PciDevice->BusNumber,\r
- PciDevice->DeviceNumber,\r
- PciDevice->FunctionNumber,\r
- EfiPciBeforeChildBusEnumeration\r
- );\r
-\r
- DEBUG((EFI_D_ERROR, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber ));\r
- Status = PciScanBus (\r
- PciDevice,\r
- (UINT8) (SecondBus),\r
- SubBusNumber,\r
- PaddedBusRange\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return EFI_DEVICE_ERROR;\r
- }\r
- }\r
-\r
- //\r
- // Set the current maximum bus number under the PPB\r
- //\r
-\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
-\r
- Status = PciRootBridgeIoWrite (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint8,\r
- Address,\r
- 1,\r
- SubBusNumber\r
- );\r
-\r
- }\r
-\r
- if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
-\r
- //\r
- // Skip sub functions, this is not a multi function device\r
- //\r
+ PMem64Base,\r
+ PMem64Bridge\r
+ );\r
\r
- Func = PCI_MAX_FUNC;\r
- }\r
- }\r
+ FreePool (AcpiConfig);\r
}\r
\r
+ //\r
+ // Destroy all the resource tree\r
+ //\r
+ DestroyResourceTree (&IoPool);\r
+ DestroyResourceTree (&Mem32Pool);\r
+ DestroyResourceTree (&PMem32Pool);\r
+ DestroyResourceTree (&Mem64Pool);\r
+ DestroyResourceTree (&PMem64Pool);\r
+\r
+ //\r
+ // Notify the resource allocation phase is to end\r
+ //\r
+ NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);\r
+\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Scan pci bus and assign bus number to the given PCI bus system.\r
+\r
+ @param Bridge Bridge device instance.\r
+ @param StartBusNumber start point.\r
+ @param SubBusNumber Point to sub bus number.\r
+ @param PaddedBusRange Customized bus number.\r
+\r
+ @retval EFI_SUCCESS Successfully scanned and assigned bus number.\r
+ @retval other Some error occurred when scanning pci bus.\r
+\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r
+\r
+**/\r
EFI_STATUS\r
-PciScanBus_WithHotPlugDeviceSupport (\r
+PciScanBus (\r
IN PCI_IO_DEVICE *Bridge,\r
IN UINT8 StartBusNumber,\r
OUT UINT8 *SubBusNumber,\r
OUT UINT8 *PaddedBusRange\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is used to assign bus number to the given PCI bus system\r
-\r
-Arguments:\r
-\r
- Bridge - A pointer to the PCI_IO_DEVICE structure.\r
- StartBusNumber - The start bus number.\r
- SubBusNumber - A pointer to the sub bus number.\r
- PaddedBusRange - A pointer to the padded bus range.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: EFI_DEVICE_ERROR - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
EFI_STATUS Status;\r
PCI_TYPE00 Pci;\r
State = 0;\r
Attributes = (EFI_HPC_PADDING_ATTRIBUTES) 0;\r
BusRange = 0;\r
+ BusPadding = FALSE;\r
+ PciDevice = NULL;\r
+ PciAddress = 0;\r
\r
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {\r
}\r
\r
DEBUG((EFI_D_ERROR, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));\r
- \r
- //\r
- // Get the PCI device information\r
- //\r
- Status = PciSearchDevice (\r
- Bridge,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func,\r
- &PciDevice\r
- );\r
-\r
- ASSERT (!EFI_ERROR (Status));\r
-\r
- PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
-\r
- if (!IS_PCI_BRIDGE (&Pci)) {\r
- //\r
- // PCI bridges will be called later\r
- // Here just need for PCI device or PCI to cardbus controller\r
- // EfiPciBeforeChildBusEnumeration for PCI Device Node\r
- //\r
- PreprocessController (\r
- PciDevice,\r
- PciDevice->BusNumber,\r
- PciDevice->DeviceNumber,\r
- PciDevice->FunctionNumber,\r
- EfiPciBeforeChildBusEnumeration\r
- );\r
- }\r
\r
- //\r
- // For Pci Hotplug controller devcie only\r
- //\r
- if (gPciHotPlugInit != NULL) {\r
+ if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
//\r
- // Check if it is a Hotplug PCI controller\r
+ // Get the PCI device information\r
//\r
- if (IsRootPciHotPlugController (PciDevice->DevicePath, &HpIndex)) {\r
-\r
- if (!gPciRootHpcData[HpIndex].Initialized) {\r
-\r
- Status = CreateEventForHpc (HpIndex, &Event);\r
+ Status = PciSearchDevice (\r
+ Bridge,\r
+ &Pci,\r
+ StartBusNumber,\r
+ Device,\r
+ Func,\r
+ &PciDevice\r
+ );\r
\r
- ASSERT (!EFI_ERROR (Status));\r
+ ASSERT (!EFI_ERROR (Status));\r
\r
- Status = gPciHotPlugInit->InitializeRootHpc (\r
- gPciHotPlugInit,\r
- gPciRootHpcPool[HpIndex].HpcDevicePath,\r
- PciAddress,\r
- Event,\r
- &State\r
- );\r
+ PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);\r
\r
- PreprocessController (\r
+ if (!IS_PCI_BRIDGE (&Pci)) {\r
+ //\r
+ // PCI bridges will be called later\r
+ // Here just need for PCI device or PCI to cardbus controller\r
+ // EfiPciBeforeChildBusEnumeration for PCI Device Node\r
+ //\r
+ PreprocessController (\r
PciDevice,\r
PciDevice->BusNumber,\r
PciDevice->DeviceNumber,\r
PciDevice->FunctionNumber,\r
EfiPciBeforeChildBusEnumeration\r
- );\r
+ );\r
+ }\r
+\r
+ //\r
+ // For Pci Hotplug controller devcie only\r
+ //\r
+ if (gPciHotPlugInit != NULL) {\r
+ //\r
+ // Check if it is a Hotplug PCI controller\r
+ //\r
+ if (IsRootPciHotPlugController (PciDevice->DevicePath, &HpIndex)) {\r
+\r
+ if (!gPciRootHpcData[HpIndex].Initialized) {\r
+\r
+ Status = CreateEventForHpc (HpIndex, &Event);\r
+\r
+ ASSERT (!EFI_ERROR (Status));\r
+\r
+ Status = gPciHotPlugInit->InitializeRootHpc (\r
+ gPciHotPlugInit,\r
+ gPciRootHpcPool[HpIndex].HpcDevicePath,\r
+ PciAddress,\r
+ Event,\r
+ &State\r
+ );\r
+\r
+ PreprocessController (\r
+ PciDevice,\r
+ PciDevice->BusNumber,\r
+ PciDevice->DeviceNumber,\r
+ PciDevice->FunctionNumber,\r
+ EfiPciBeforeChildBusEnumeration\r
+ );\r
+ }\r
}\r
}\r
}\r
if (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)) {\r
//\r
// For PPB\r
- // Get the bridge information\r
//\r
- BusPadding = FALSE;\r
- if (gPciHotPlugInit != NULL) {\r
+ if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
+ //\r
+ // If Hot Plug is not supported,\r
+ // get the bridge information\r
+ //\r
+ Status = PciSearchDevice (\r
+ Bridge,\r
+ &Pci,\r
+ StartBusNumber,\r
+ Device,\r
+ Func,\r
+ &PciDevice\r
+ );\r
\r
- if (IsRootPciHotPlugBus (PciDevice->DevicePath, &HpIndex)) {\r
-\r
- //\r
- // If it is initialized, get the padded bus range\r
- //\r
- Status = gPciHotPlugInit->GetResourcePadding (\r
- gPciHotPlugInit,\r
- gPciRootHpcPool[HpIndex].HpbDevicePath,\r
- PciAddress,\r
- &State,\r
- (VOID **) &Descriptors,\r
- &Attributes\r
- );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ } else {\r
+ //\r
+ // If Hot Plug is supported,\r
+ // Get the bridge information\r
+ //\r
+ BusPadding = FALSE;\r
+ if (gPciHotPlugInit != NULL) {\r
+\r
+ if (IsRootPciHotPlugBus (PciDevice->DevicePath, &HpIndex)) {\r
+\r
+ //\r
+ // If it is initialized, get the padded bus range\r
+ //\r
+ Status = gPciHotPlugInit->GetResourcePadding (\r
+ gPciHotPlugInit,\r
+ gPciRootHpcPool[HpIndex].HpbDevicePath,\r
+ PciAddress,\r
+ &State,\r
+ (VOID **) &Descriptors,\r
+ &Attributes\r
+ );\r
\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- BusRange = 0;\r
- Status = PciGetBusRange (\r
- &Descriptors,\r
- NULL,\r
- NULL,\r
- &BusRange\r
- );\r
+ BusRange = 0;\r
+ Status = PciGetBusRange (\r
+ &Descriptors,\r
+ NULL,\r
+ NULL,\r
+ &BusRange\r
+ );\r
\r
- gBS->FreePool (Descriptors);\r
+ FreePool (Descriptors);\r
\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- BusPadding = TRUE;\r
+ BusPadding = TRUE;\r
+ }\r
}\r
}\r
\r
//\r
// Add feature to support customized secondary bus number\r
//\r
- if (*SubBusNumber == 0) { \r
+ if (*SubBusNumber == 0) {\r
*SubBusNumber = *PaddedBusRange;\r
*PaddedBusRange = 0;\r
}\r
SecondBus = *SubBusNumber;\r
\r
Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);\r
\r
Status = PciRootBridgeIoWrite (\r
PciRootBridgeIo,\r
if (IS_PCI_BRIDGE (&Pci)) {\r
\r
//\r
- // Initialize SubBusNumber to Maximum bus number\r
+ // Temporarily initialize SubBusNumber to maximum bus number to ensure the\r
+ // PCI configuration transaction to go through any PPB\r
//\r
Register = 0xFF;\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
Status = PciRootBridgeIoWrite (\r
PciRootBridgeIo,\r
&Pci,\r
EfiPciBeforeChildBusEnumeration\r
);\r
\r
- DEBUG((EFI_D_ERROR, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber ));\r
+ DEBUG((EFI_D_ERROR, "Scan PPB(%02d,%02d,%02d)\n", PciDevice->BusNumber, PciDevice->DeviceNumber,PciDevice->FunctionNumber));\r
Status = PciScanBus (\r
PciDevice,\r
(UINT8) (SecondBus),\r
SubBusNumber,\r
PaddedBusRange\r
);\r
-\r
if (EFI_ERROR (Status)) {\r
- return EFI_DEVICE_ERROR;\r
+ return Status;\r
}\r
}\r
\r
- if (BusPadding) {\r
+ if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport) && BusPadding) {\r
//\r
// Ensure the device is enabled and initialized\r
//\r
if ((Attributes == EfiPaddingPciRootBridge) &&\r
- (State & EFI_HPC_STATE_ENABLED) &&\r
- (State & EFI_HPC_STATE_INITIALIZED) ) {\r
+ (State & EFI_HPC_STATE_ENABLED) != 0 &&\r
+ (State & EFI_HPC_STATE_INITIALIZED) != 0) {\r
*PaddedBusRange = (UINT8) ((UINT8) (BusRange) +*PaddedBusRange);\r
} else {\r
*SubBusNumber = (UINT8) ((UINT8) (BusRange) +*SubBusNumber);\r
//\r
// Set the current maximum bus number under the PPB\r
//\r
- Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
+ Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
\r
Status = PciRootBridgeIoWrite (\r
PciRootBridgeIo,\r
//\r
// Skip sub functions, this is not a multi function device\r
//\r
+\r
Func = PCI_MAX_FUNC;\r
}\r
-\r
}\r
}\r
\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Process Option Rom on the specified root bridge.\r
+\r
+ @param Bridge Pci root bridge device instance.\r
+\r
+ @retval EFI_SUCCESS Success process.\r
+ @retval other Some error occurred when processing Option Rom on the root bridge.\r
+\r
+**/\r
EFI_STATUS\r
PciRootBridgeP2CProcess (\r
IN PCI_IO_DEVICE *Bridge\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Process Option Rom on this host bridge\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
LIST_ENTRY *CurrentLink;\r
PCI_IO_DEVICE *Temp;\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
\r
- while (CurrentLink && CurrentLink != &Bridge->ChildList) {\r
+ while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
\r
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
\r
if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {\r
\r
- if (gPciHotPlugInit && Temp->Allocated) {\r
+ if (gPciHotPlugInit != NULL && Temp->Allocated && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
\r
//\r
// Raise the EFI_IOB_PCI_HPC_INIT status code\r
return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Process Option Rom on the specified host bridge.\r
+\r
+ @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r
+\r
+ @retval EFI_SUCCESS Success process.\r
+ @retval EFI_NOT_FOUND Can not find the root bridge instance.\r
+ @retval other Some error occurred when processing Option Rom on the host bridge.\r
+\r
+**/\r
EFI_STATUS\r
PciHostBridgeP2CProcess (\r
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: PciResAlloc - add argument and description to function comment\r
-// TODO: EFI_NOT_FOUND - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
EFI_HANDLE RootBridgeHandle;\r
PCI_IO_DEVICE *RootBridgeDev;\r
}\r
\r
Status = PciRootBridgeP2CProcess (RootBridgeDev);\r
-\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-PciHostBridgeEnumerator (\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
This function is used to enumerate the entire host bridge\r
- in a given platform\r
+ in a given platform.\r
\r
-Arguments:\r
+ @param PciResAlloc A pointer to the PCI Host Resource Allocation protocol.\r
\r
- PciResAlloc - A pointer to the resource allocate protocol.\r
+ @retval EFI_SUCCESS Successfully enumerated the host bridge.\r
+ @retval EFI_OUT_OF_RESOURCES No enough memory available.\r
+ @retval other Some error occurred when enumerating the host bridge.\r
\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+EFI_STATUS\r
+PciHostBridgeEnumerator (\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
+ )\r
{\r
EFI_HANDLE RootBridgeHandle;\r
PCI_IO_DEVICE *RootBridgeDev;\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
UINT16 MinBus;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
+ UINT8 StartBusNumber;\r
+ LIST_ENTRY RootBridgeList;\r
+ LIST_ENTRY *Link;\r
+\r
+ if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
+ InitializeHotPlugSupport ();\r
+ }\r
\r
- InitializeHotPlugSupport ();\r
+ InitializeListHead (&RootBridgeList);\r
\r
//\r
// Notify the bus allocation phase is about to start\r
//\r
// Enumerate all the buses under this root bridge\r
//\r
-\r
Status = PciRootBridgeEnumerator (\r
PciResAlloc,\r
RootBridgeDev\r
);\r
\r
- DestroyRootBridge (RootBridgeDev);\r
+ if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
+ InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));\r
+ } else {\r
+ DestroyRootBridge (RootBridgeDev);\r
+ }\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
//\r
NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
\r
- if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
-\r
- if (gPciHotPlugInit != NULL) {\r
+ if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
+ //\r
+ // Reset all assigned PCI bus number in all PPB\r
+ //\r
+ RootBridgeHandle = NULL;\r
+ Link = GetFirstNode (&RootBridgeList);\r
+ while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&\r
+ (!IsNull (&RootBridgeList, Link))) {\r
+ RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);\r
//\r
- // Wait for all HPC initialized\r
+ // Get the Bus information\r
//\r
- Status = AllRootHPCInitialized (STALL_1_SECOND * 15);\r
-\r
+ Status = PciResAlloc->StartBusEnumeration (\r
+ PciResAlloc,\r
+ RootBridgeHandle,\r
+ (VOID **) &Configuration\r
+ );\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
//\r
- // Notify the bus allocation phase is about to start for the 2nd time\r
+ // Get the bus number to start with\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
+ StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
\r
- DEBUG((EFI_D_ERROR, "PCI Bus Second Scanning\n")); \r
- RootBridgeHandle = NULL;\r
- while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
+ ResetAllPpbBusNumber (\r
+ RootBridgeDev,\r
+ StartBusNumber\r
+ );\r
\r
- //\r
- // if a root bridge instance is found, create root bridge device for it\r
- //\r
+ FreePool (Configuration);\r
+ Link = GetNextNode (&RootBridgeList, Link);\r
+ DestroyRootBridge (RootBridgeDev);\r
+ }\r
\r
- RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
+ //\r
+ // Wait for all HPC initialized\r
+ //\r
+ Status = AllRootHPCInitialized (STALL_1_SECOND * 15);\r
\r
- if (RootBridgeDev == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
\r
- //\r
- // Enumerate all the buses under this root bridge\r
- //\r
+ //\r
+ // Notify the bus allocation phase is about to start for the 2nd time\r
+ //\r
+ NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);\r
\r
- Status = PciRootBridgeEnumerator (\r
- PciResAlloc,\r
- RootBridgeDev\r
- );\r
+ DEBUG((EFI_D_ERROR, "PCI Bus Second Scanning\n"));\r
+ RootBridgeHandle = NULL;\r
+ while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
\r
- DestroyRootBridge (RootBridgeDev);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
+ //\r
+ // if a root bridge instance is found, create root bridge device for it\r
+ //\r
+ RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
+\r
+ if (RootBridgeDev == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
}\r
\r
//\r
- // Notify the bus allocation phase is to end for the 2nd time\r
+ // Enumerate all the buses under this root bridge\r
//\r
- NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
+ Status = PciRootBridgeEnumerator (\r
+ PciResAlloc,\r
+ RootBridgeDev\r
+ );\r
+\r
+ DestroyRootBridge (RootBridgeDev);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
}\r
+\r
+ //\r
+ // Notify the bus allocation phase is to end for the 2nd time\r
+ //\r
+ NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
}\r
\r
//\r
//\r
// if a root bridge instance is found, create root bridge device for it\r
//\r
-\r
RootBridgeDev = CreateRootBridge (RootBridgeHandle);\r
\r
if (RootBridgeDev == NULL) {\r
This function check the incompatiblilites on PCI device. Return the register\r
value.\r
\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
+ @param PciRootBridgeIo PCI root bridge io protocol instance.\r
+ @param PciIo PCI IO protocol instance.\r
+ @param PciDeviceInfo PCI device information.\r
@param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Address The address within the PCI configuration space for the PCI controller.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.\r
+ @retval other Some error occurred when reading PCI device configuration space\r
+ or checking incompatibility.\r
\r
**/\r
-STATIC\r
EFI_STATUS\r
ReadConfigData (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
UINT8 *Pointer;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ ASSERT (Buffer != NULL);\r
\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {\r
//\r
- // check access compatibility at first time\r
+ // Check access compatibility at first time\r
//\r
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Address & 0xff, Width, &PciRegisterAccessData);\r
\r
if (Status == EFI_SUCCESS) {\r
//\r
- // there exist incompatibility on this operation\r
+ // There exists incompatibility on this operation\r
//\r
AccessWidth = Width;\r
\r
Stride = 0;\r
Pointer = (UINT8 *) &TempBuffer;\r
\r
- while (1) {\r
+ while (TRUE) {\r
\r
if (PciRootBridgeIo != NULL) {\r
Status = PciRootBridgeIo->Pci.Read (\r
return Status;\r
}\r
\r
- Stride = 1 << AccessWidth;\r
+ Stride = (UINTN)1 << AccessWidth;\r
AccessAddress += Stride;\r
- if (AccessAddress >= (Address + (1 << Width))) {\r
+ if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
- // if all datas have been read, exist\r
+ // If all datas have been read, exit\r
//\r
break;\r
}\r
\r
if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {\r
//\r
- // if current offset doesn't reach the end\r
+ // If current offset doesn't reach the end\r
//\r
continue;\r
}\r
\r
- FreePool (PciRegisterAccessData);\r
-\r
//\r
- // continue checking access incompatibility\r
+ // Continue checking access incompatibility\r
//\r
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);\r
if (Status == EFI_SUCCESS) {\r
}\r
}\r
\r
- FreePool (PciRegisterAccessData);\r
-\r
switch (Width) {\r
case EfiPciWidthUint8:\r
* (UINT8 *) Buffer = (UINT8) TempBuffer;\r
\r
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
@param AccessType Access type, READ or WRITE.\r
- @Param Address The address within the PCI configuration space.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Address The address within the PCI configuration space.\r
@param Buffer Store the register data.\r
\r
@retval EFI_SUCCESS The data has been updated.\r
+ @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.\r
+ @retval other Some error occurred when checking incompatibility.\r
\r
**/\r
-STATIC\r
EFI_STATUS\r
UpdateConfigData (\r
IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
UINT32 OrValue;\r
UINT32 TempValue;\r
\r
+ ASSERT (Buffer != NULL);\r
+\r
//\r
- // check register value incompatibility\r
+ // Check register value incompatibility\r
//\r
Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Address & 0xff, &PciRegisterData);\r
-\r
if (Status == EFI_SUCCESS) {\r
\r
AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Address & 0x3) * 8);\r
default:\r
return EFI_UNSUPPORTED;\r
}\r
-\r
- FreePool (PciRegisterData);\r
}\r
\r
return Status;\r
This function check the incompatiblilites on PCI device, and write date\r
into register.\r
\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
+ @param PciRootBridgeIo PCI root bridge io instance.\r
+ @param PciIo PCI IO protocol instance.\r
+ @param PciDeviceInfo PCI device information.\r
@param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Address The address within the PCI configuration space for the PCI controller.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval other Some error occurred when writing PCI device information\r
+ or checking incompatibility.\r
\r
**/\r
-STATIC\r
EFI_STATUS\r
WriteConfigData (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
UINTN Shift;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ ASSERT (Buffer != NULL);\r
\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {\r
//\r
- // check access compatibility at first time\r
+ // Check access compatibility at first time\r
//\r
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Address & 0xff, Width, &PciRegisterAccessData);\r
\r
if (Status == EFI_SUCCESS) {\r
//\r
- // there exist incompatibility on this operation\r
+ // There exists incompatibility on this operation\r
//\r
AccessWidth = Width;\r
\r
Pointer = (UINT8 *) &Buffer;\r
Data = * (UINT64 *) Buffer;\r
\r
- while (1) {\r
+ while (TRUE) {\r
\r
if (AccessWidth > Width) {\r
//\r
- // if actual access width is larger than orignal one, additional data need to be read back firstly\r
+ // If actual access width is larger than orignal one, additional data need to be read back firstly\r
//\r
Status = ReadConfigData (PciRootBridgeIo, PciIo, PciDeviceInfo, AccessWidth, AccessAddress, &Data);\r
if (Status != EFI_SUCCESS) {\r
}\r
\r
//\r
- // check data read incompatibility\r
+ // Check data read incompatibility\r
//\r
UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);\r
\r
}\r
\r
//\r
- // check data write incompatibility\r
+ // Check data write incompatibility\r
//\r
UpdateConfigData (PciDeviceInfo, PCI_REGISTER_WRITE, AccessWidth, MultU64x32 (AccessAddress, 0xff), &Data);\r
}\r
\r
Data = RShiftU64 (Data, ((1 << AccessWidth) * 8));\r
\r
- Stride = 1 << AccessWidth;\r
+ Stride = (UINTN)1 << AccessWidth;\r
AccessAddress += Stride;\r
- if (AccessAddress >= (Address + (1 << Width))) {\r
+ if (AccessAddress >= (Address + LShiftU64 (1ULL, (UINTN)Width))) {\r
//\r
- // if all datas have been written, exist\r
+ // If all datas have been written, exit\r
//\r
break;\r
}\r
\r
if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {\r
//\r
- // if current offset doesn't reach the end\r
+ // If current offset doesn't reach the end\r
//\r
continue;\r
}\r
\r
- FreePool (PciRegisterAccessData);\r
-\r
//\r
- // continue checking access incompatibility\r
+ // Continue checking access incompatibility\r
//\r
Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);\r
if (Status == EFI_SUCCESS) {\r
}\r
};\r
\r
- FreePool (PciRegisterAccessData);\r
-\r
return Status;\r
}\r
\r
\r
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Pci PCI device configuration space.\r
+ @param Address The address within the PCI configuration space for the PCI controller.\r
@param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
\r
@retval EFI_SUCCESS Pci device device information has been abstracted.\r
+ @retval EFI_NOT_FOUND Cannot found the specified PCI device.\r
+ @retval other Some error occurred when reading PCI device information.\r
\r
**/\r
-STATIC\r
EFI_STATUS\r
GetPciDeviceDeviceInfo (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
PCI_IO_DEVICE *PciIoDevice;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ ASSERT (PciDeviceInfo != NULL);\r
\r
if (PciIo != NULL) {\r
PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
\r
//\r
- // get pointer to PCI_TYPE00 from PciIoDevice\r
+ // Get pointer to PCI_TYPE00 from PciIoDevice\r
//\r
Pci = &PciIoDevice->Pci;\r
}\r
\r
if (Pci == NULL) {\r
//\r
- // while PCI_TYPE00 hasn't been gotten, read PCI device device information directly\r
+ // While PCI_TYPE00 hasn't been gotten, read PCI device device information directly\r
//\r
PciAddress = Address & 0xffffffffffffff00ULL;\r
Status = PciRootBridgeIo->Pci.Read (\r
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.\r
@param Pci A pointer to PCI_TYPE00.\r
@param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Count The number of unit to be read.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_UNSUPPORTED Buffer is NULL.\r
+ @retval other Some error occurred when reading PCI configuration space.\r
\r
**/\r
-STATIC\r
EFI_STATUS\r
PciIncompatibilityCheckRead (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
IN UINT64 Address,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
-)\r
+ )\r
{\r
EFI_STATUS Status;\r
EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
UINT32 Stride;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ if (Buffer == NULL) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
\r
//\r
// get PCI device device information\r
//\r
// update the data read from configuration register\r
//\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Address & 0xff, Buffer);\r
}\r
}\r
@param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.\r
@param Pci A pointer to PCI_TYPE00.\r
@param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Count The number of unit to be write.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ Buffer is NULL.\r
+ @retval other Some error occurred when writing PCI configuration space.\r
\r
**/\r
-STATIC\r
EFI_STATUS\r
PciIncompatibilityCheckWrite (\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
IN UINT64 Address,\r
IN UINTN Count,\r
IN OUT VOID *Buffer\r
-)\r
+ )\r
{\r
EFI_STATUS Status;\r
EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
UINT64 Data;\r
\r
ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
+ if (Buffer == NULL) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
\r
//\r
- // get PCI device device information\r
+ // Get PCI device device information\r
//\r
Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Address, &PciDeviceInfo);\r
if (Status != EFI_SUCCESS) {\r
}\r
\r
//\r
- // update the data writen into configuration register\r
+ // Update the data writen into configuration register\r
//\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Address & 0xff, &Data);\r
}\r
\r
//\r
- // write configuration register\r
+ // Write configuration register\r
//\r
Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Address, &Data);\r
\r
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param Pci A pointer to PCI_TYPE00.\r
@param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Count The number of unit to be read.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
EFI_STATUS\r
IN OUT VOID *Buffer\r
)\r
{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) {\r
- //\r
- // if PCI incompatibility check enabled\r
- //\r
- return PciIncompatibilityCheckRead (\r
- PciRootBridgeIo,\r
- NULL,\r
- Pci,\r
- (UINTN) Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ EFI_STATUS Status;\r
+\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {\r
+ //\r
+ // If PCI incompatibility check enabled\r
+ //\r
+ Status = PciIncompatibilityCheckRead (\r
+ PciRootBridgeIo,\r
+ NULL,\r
+ Pci,\r
+ (UINTN) Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
+ if (Status == EFI_UNSUPPORTED) {\r
+ return EFI_INVALID_PARAMETER;\r
+ } else {\r
+ return Status;\r
+ }\r
} else {\r
return PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ PciRootBridgeIo,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
}\r
}\r
\r
@param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
@param Pci A pointer to PCI_TYPE00.\r
@param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Count The number of unit to be read.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
EFI_STATUS\r
IN OUT VOID *Buffer\r
)\r
{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) {\r
- //\r
- // if PCI incompatibility check enabled\r
- //\r
- return PciIncompatibilityCheckWrite (\r
- PciRootBridgeIo,\r
- NULL,\r
- Pci,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ EFI_STATUS Status;\r
+\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {\r
+ //\r
+ // If PCI incompatibility check enabled\r
+ //\r
+ Status = PciIncompatibilityCheckWrite (\r
+ PciRootBridgeIo,\r
+ NULL,\r
+ Pci,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
+ if (Status == EFI_UNSUPPORTED) {\r
+ return EFI_INVALID_PARAMETER;\r
+ } else {\r
+ return Status;\r
+ }\r
\r
} else {\r
return PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ PciRootBridgeIo,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
}\r
}\r
\r
\r
@param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
@param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Address The address within the PCI configuration space for the PCI controller.\r
+ @param Count The number of unit to be read.\r
@param Buffer For read operations, the destination buffer to store the results. For\r
write operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
\r
**/\r
EFI_STATUS\r
IN OUT VOID *Buffer\r
)\r
{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) {\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {\r
//\r
- // if PCI incompatibility check enabled\r
+ // If PCI incompatibility check enabled\r
//\r
return PciIncompatibilityCheckRead (\r
- NULL,\r
- PciIo,\r
- NULL,\r
- (UINTN) Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ NULL,\r
+ PciIo,\r
+ NULL,\r
+ (UINTN) Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
} else {\r
return PciIo->Pci.Read (\r
- PciIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ PciIo,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
}\r
}\r
\r
/**\r
Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
\r
- @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
- @param Width Signifies the width of the memory operations.\r
- @Param Address The address within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
+ If PCI incompatibility check is enabled, do incompatibility check.\r
+\r
+ @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
+ @param Width Signifies the width of the memory operations.\r
+ @param Offset The offset within the PCI configuration space for the PCI controller.\r
+ @param Count The number of PCI configuration operations to perform.\r
+ @param Buffer For read operations, the destination buffer to store the results. For write\r
+ operations, the source buffer to write data from.\r
\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
+ @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
+ valid for the PCI configuration header of the PCI controller.\r
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
\r
**/\r
EFI_STATUS\r
IN OUT VOID *Buffer\r
)\r
{\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) {\r
-\r
+ if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {\r
//\r
- // if PCI incompatibility check enabled\r
+ // If PCI incompatibility check enabled\r
//\r
return PciIncompatibilityCheckWrite (\r
- NULL,\r
- PciIo,\r
- NULL,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ NULL,\r
+ PciIo,\r
+ NULL,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
\r
} else {\r
return PciIo->Pci.Write (\r
- PciIo,\r
- Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ PciIo,\r
+ Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
}\r
}\r
+\r
projects / mirror_edk2.git / blobdiff