-/**@file\r
+/** @file\r
+ PCI resouces support functions implemntation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2007, Intel Corporation\r
+Copyright (c) 2006 - 2009, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
**/\r
\r
-#include "pcibus.h"\r
-#include "PciResourceSupport.h"\r
-#include "PciCommand.h"\r
+#include "PciBus.h"\r
\r
-EFI_STATUS\r
+/**\r
+ The function is used to skip VGA range.\r
+\r
+ @param Start Returned start address including VGA range.\r
+ @param Length The length of VGA range.\r
+\r
+**/\r
+VOID\r
SkipVGAAperture (\r
OUT UINT64 *Start,\r
IN UINT64 Length\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- The function is used to skip VGA range\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Start - add argument and description to function comment\r
-// TODO: Length - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
UINT64 Original;\r
UINT64 Mask;\r
UINT64 StartOffset;\r
UINT64 LimitOffset;\r
\r
+ ASSERT (Start != NULL);\r
//\r
// For legacy VGA, bit 10 to bit 15 is not decoded\r
//\r
if (LimitOffset >= VGABASE1) {\r
*Start = *Start - StartOffset + VGALIMIT2 + 1;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
+/**\r
+ This function is used to skip ISA aliasing aperture.\r
+\r
+ @param Start Returned start address including ISA aliasing aperture.\r
+ @param Length The length of ISA aliasing aperture.\r
+\r
+**/\r
+VOID\r
SkipIsaAliasAperture (\r
OUT UINT64 *Start,\r
IN UINT64 Length\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function is used to skip ISA aliasing aperture\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Start - add argument and description to function comment\r
-// TODO: Length - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
\r
UINT64 Original;\r
UINT64 StartOffset;\r
UINT64 LimitOffset;\r
\r
+ ASSERT (Start != NULL);\r
+\r
//\r
// For legacy ISA, bit 10 to bit 15 is not decoded\r
//\r
if (LimitOffset >= ISABASE) {\r
*Start = *Start - StartOffset + ISALIMIT + 1;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-InsertResourceNode (\r
- PCI_RESOURCE_NODE *Bridge,\r
- PCI_RESOURCE_NODE *ResNode\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
This function inserts a resource node into the resource list.\r
The resource list is sorted in descend order.\r
\r
-Arguments:\r
+ @param Bridge PCI resource node for bridge.\r
+ @param ResNode Resource node want to be inserted.\r
\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: ResNode - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+InsertResourceNode (\r
+ IN OUT PCI_RESOURCE_NODE *Bridge,\r
+ IN PCI_RESOURCE_NODE *ResNode\r
+ )\r
{\r
LIST_ENTRY *CurrentLink;\r
PCI_RESOURCE_NODE *Temp;\r
UINT64 ResNodeAlignRest;\r
UINT64 TempAlignRest;\r
\r
+ ASSERT (Bridge != NULL);\r
+ ASSERT (ResNode != NULL);\r
+\r
InsertHeadList (&Bridge->ChildList, &ResNode->Link);\r
\r
CurrentLink = Bridge->ChildList.ForwardLink->ForwardLink;\r
\r
CurrentLink = ResNode->Link.ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-MergeResourceTree (\r
- PCI_RESOURCE_NODE *Dst,\r
- PCI_RESOURCE_NODE *Res,\r
- BOOLEAN TypeMerge\r
- )\r
-/*++\r
-\r
-Routine Description:\r
+/**\r
+ This routine is used to merge two different resource trees in need of\r
+ resoure degradation.\r
\r
- This routine is used to merge two different resource tree in need of\r
- resoure degradation. For example, if a upstream PPB doesn't support,\r
+ For example, if an upstream PPB doesn't support,\r
prefetchable memory decoding, the PCI bus driver will choose to call this function\r
to merge prefectchable memory resource list into normal memory list.\r
\r
If the TypeMerge is TRUE, Res resource type is changed to the type of destination resource\r
type.\r
+ If Dst is NULL or Res is NULL, ASSERT ().\r
\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
+ @param Dst Point to destination resource tree.\r
+ @param Res Point to source resource tree.\r
+ @param TypeMerge If the TypeMerge is TRUE, Res resource type is changed to the type of\r
+ destination resource type.\r
\r
---*/\r
-// TODO: Dst - add argument and description to function comment\r
-// TODO: Res - add argument and description to function comment\r
-// TODO: TypeMerge - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+MergeResourceTree (\r
+ IN PCI_RESOURCE_NODE *Dst,\r
+ IN PCI_RESOURCE_NODE *Res,\r
+ IN BOOLEAN TypeMerge\r
+ )\r
{\r
\r
LIST_ENTRY *CurrentLink;\r
PCI_RESOURCE_NODE *Temp;\r
\r
+ ASSERT (Dst != NULL);\r
+ ASSERT (Res != NULL);\r
+\r
while (!IsListEmpty (&Res->ChildList)) {\r
CurrentLink = Res->ChildList.ForwardLink;\r
\r
\r
RemoveEntryList (CurrentLink);\r
InsertResourceNode (Dst, Temp);\r
-\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-CalculateApertureIo16 (\r
- IN PCI_RESOURCE_NODE *Bridge\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
This function is used to calculate the IO16 aperture\r
for a bridge.\r
\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
+ @param Bridge PCI resource node for bridge.\r
\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+CalculateApertureIo16 (\r
+ IN PCI_RESOURCE_NODE *Bridge\r
+ )\r
{\r
-\r
- UINT64 Aperture;\r
- LIST_ENTRY *CurrentLink;\r
- PCI_RESOURCE_NODE *Node;\r
- UINT64 offset;\r
- BOOLEAN IsaEnable;\r
- BOOLEAN VGAEnable;\r
+ EFI_STATUS Status;\r
+ UINT64 Aperture;\r
+ LIST_ENTRY *CurrentLink;\r
+ PCI_RESOURCE_NODE *Node;\r
+ UINT64 Offset;\r
+ BOOLEAN IsaEnable;\r
+ BOOLEAN VGAEnable;\r
+ EFI_PCI_PLATFORM_POLICY PciPolicy;\r
\r
//\r
// Always assume there is ISA device and VGA device on the platform\r
IsaEnable = FALSE;\r
VGAEnable = FALSE;\r
\r
- if (FeaturePcdGet (PcdPciIsaEnable)){\r
- IsaEnable = TRUE;\r
- }\r
-\r
- if (FeaturePcdGet (PcdPciVgaEnable)){\r
- VGAEnable = TRUE;\r
+ //\r
+ // Check PciPlatform policy\r
+ //\r
+ if (gPciPlatformProtocol != NULL) {\r
+ Status = gPciPlatformProtocol->GetPlatformPolicy (\r
+ gPciPlatformProtocol,\r
+ &PciPolicy\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) {\r
+ IsaEnable = TRUE;\r
+ }\r
+ if ((PciPolicy & EFI_RESERVE_VGA_IO_ALIAS) != 0) {\r
+ VGAEnable = TRUE;\r
+ }\r
+ }\r
}\r
\r
Aperture = 0;\r
\r
- if (!Bridge) {\r
- return EFI_SUCCESS;\r
+ if (Bridge == NULL) {\r
+ return ;\r
}\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
//\r
// Consider the aperture alignment\r
//\r
- offset = Aperture & (Node->Alignment);\r
+ Offset = Aperture & (Node->Alignment);\r
\r
- if (offset) {\r
+ if (Offset != 0) {\r
\r
- Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+ Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
\r
}\r
\r
// If both of them are enabled, then the IO resource would\r
// become too limited to meet the requirement of most of devices.\r
//\r
-\r
if (IsaEnable || VGAEnable) {\r
if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci)) && !IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
//\r
if (IsaEnable) {\r
SkipIsaAliasAperture (\r
&Aperture,\r
- Node->Length \r
+ Node->Length\r
);\r
- offset = Aperture & (Node->Alignment);\r
- if (offset) {\r
- Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+ Offset = Aperture & (Node->Alignment);\r
+ if (Offset != 0) {\r
+ Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
}\r
} else if (VGAEnable) {\r
SkipVGAAperture (\r
&Aperture,\r
Node->Length\r
);\r
- offset = Aperture & (Node->Alignment);\r
- if (offset) {\r
- Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+ Offset = Aperture & (Node->Alignment);\r
+ if (Offset != 0) {\r
+ Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
}\r
}\r
}\r
// At last, adjust the aperture with the bridge's\r
// alignment\r
//\r
- offset = Aperture & (Bridge->Alignment);\r
+ Offset = Aperture & (Bridge->Alignment);\r
\r
- if (offset) {\r
- Aperture = Aperture + (Bridge->Alignment + 1) - offset;\r
+ if (Offset != 0) {\r
+ Aperture = Aperture + (Bridge->Alignment + 1) - Offset;\r
}\r
\r
Bridge->Length = Aperture;\r
Bridge->Alignment = Node->Alignment;\r
}\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-CalculateResourceAperture (\r
- IN PCI_RESOURCE_NODE *Bridge\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
+/**\r
This function is used to calculate the resource aperture\r
- for a given bridge device\r
+ for a given bridge device.\r
\r
-Arguments:\r
+ @param Bridge PCI resouce node for given bridge device.\r
\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+CalculateResourceAperture (\r
+ IN PCI_RESOURCE_NODE *Bridge\r
+ )\r
{\r
UINT64 Aperture;\r
LIST_ENTRY *CurrentLink;\r
PCI_RESOURCE_NODE *Node;\r
\r
- UINT64 offset;\r
+ UINT64 Offset;\r
\r
Aperture = 0;\r
\r
- if (!Bridge) {\r
- return EFI_SUCCESS;\r
+ if (Bridge == NULL) {\r
+ return ;\r
}\r
\r
if (Bridge->ResType == PciBarTypeIo16) {\r
- return CalculateApertureIo16 (Bridge);\r
+\r
+ CalculateApertureIo16 (Bridge);\r
+ return ;\r
}\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
//\r
// Apply padding resource if available\r
//\r
- \r
- offset = Aperture & (Node->Alignment);\r
+ Offset = Aperture & (Node->Alignment);\r
\r
- if (offset) {\r
+ if (Offset != 0) {\r
\r
- Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+ Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
\r
}\r
\r
//\r
// Consider the aperture alignment\r
//\r
- \r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
\r
// At last, adjust the aperture with the bridge's\r
// alignment\r
//\r
- offset = Aperture & (Bridge->Alignment);\r
- if (offset) {\r
- Aperture = Aperture + (Bridge->Alignment + 1) - offset;\r
+ Offset = Aperture & (Bridge->Alignment);\r
+ if (Offset != 0) {\r
+ Aperture = Aperture + (Bridge->Alignment + 1) - Offset;\r
}\r
\r
//\r
if (Bridge->Length < Aperture) {\r
Bridge->Length = Aperture;\r
}\r
- \r
+\r
//\r
// At last, adjust the bridge's alignment to the first child's alignment\r
// if the bridge has at least one child\r
Bridge->Alignment = Node->Alignment;\r
}\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-GetResourceFromDevice (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
+/**\r
+ Get IO/Memory resource infor for given PCI device.\r
\r
- None\r
+ @param PciDev Pci device instance.\r
+ @param IoNode Resource info node for IO .\r
+ @param Mem32Node Resource info node for 32-bit memory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
+ @param Mem64Node Resource info node for 64-bit memory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
---*/\r
-// TODO: PciDev - add argument and description to function comment\r
-// TODO: IoNode - add argument and description to function comment\r
-// TODO: Mem32Node - add argument and description to function comment\r
-// TODO: PMem32Node - add argument and description to function comment\r
-// TODO: Mem64Node - add argument and description to function comment\r
-// TODO: PMem64Node - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+GetResourceFromDevice (\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN OUT PCI_RESOURCE_NODE *IoNode,\r
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem64Node\r
+ )\r
{\r
\r
UINT8 Index;\r
if (!ResourceRequested) {\r
PciDev->Allocated = TRUE;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ This function is used to create a resource node.\r
+\r
+ @param PciDev Pci device instance.\r
+ @param Length Length of Io/Memory resource.\r
+ @param Alignment Alignment of resource.\r
+ @param Bar Bar index.\r
+ @param ResType Type of resource: IO/Memory.\r
+ @param ResUsage Resource usage.\r
+\r
+ @return PCI resource node created for given PCI device.\r
+ NULL means PCI resource node is not created.\r
+\r
+**/\r
PCI_RESOURCE_NODE *\r
CreateResourceNode (\r
IN PCI_IO_DEVICE *PciDev,\r
IN PCI_BAR_TYPE ResType,\r
IN PCI_RESOURCE_USAGE ResUsage\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function is used to create a resource node\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: PciDev - add argument and description to function comment\r
-// TODO: Length - add argument and description to function comment\r
-// TODO: Alignment - add argument and description to function comment\r
-// TODO: Bar - add argument and description to function comment\r
-// TODO: ResType - add argument and description to function comment\r
-// TODO: ResUsage - add argument and description to function comment\r
{\r
PCI_RESOURCE_NODE *Node;\r
\r
Node = NULL;\r
\r
- Node = AllocatePool (sizeof (PCI_RESOURCE_NODE));\r
+ Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));\r
ASSERT (Node != NULL);\r
if (Node == NULL) {\r
return NULL;\r
}\r
\r
- ZeroMem (Node, sizeof (PCI_RESOURCE_NODE));\r
-\r
Node->Signature = PCI_RESOURCE_SIGNATURE;\r
Node->PciDev = PciDev;\r
Node->Length = Length;\r
Node->Alignment = Alignment;\r
- if(((ResType == PciBarTypeIo16) || (ResType == PciBarTypeIo32)) && ( Alignment == 0x0FFF))\r
- {\r
- if((PciDev->Decodes & EFI_BRIDGE_IOEN1K_DECODE_SUPPORTED) == EFI_BRIDGE_IOEN1K_DECODE_SUPPORTED)\r
- Node->Alignment = 0x3FF;\r
- else\r
- Node->Alignment = 0xFFF;\r
- }\r
Node->Bar = Bar;\r
Node->ResType = ResType;\r
Node->Reserved = FALSE;\r
Node->ResourceUsage = ResUsage;\r
InitializeListHead (&Node->ChildList);\r
+\r
return Node;\r
}\r
\r
-EFI_STATUS\r
-CreateResourceMap (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN PCI_RESOURCE_NODE *IoNode,\r
- IN PCI_RESOURCE_NODE *Mem32Node,\r
- IN PCI_RESOURCE_NODE *PMem32Node,\r
- IN PCI_RESOURCE_NODE *Mem64Node,\r
- IN PCI_RESOURCE_NODE *PMem64Node\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This routine is used to extract resource request from\r
+/**\r
+ This function is used to extract resource request from\r
device node list.\r
\r
-Arguments:\r
-\r
-Returns:\r
+ @param Bridge Pci device instance.\r
+ @param IoNode Resource info node for IO.\r
+ @param Mem32Node Resource info node for 32-bit memory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
+ @param Mem64Node Resource info node for 64-bit memory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
- None\r
-\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: IoNode - add argument and description to function comment\r
-// TODO: Mem32Node - add argument and description to function comment\r
-// TODO: PMem32Node - add argument and description to function comment\r
-// TODO: Mem64Node - add argument and description to function comment\r
-// TODO: PMem64Node - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+CreateResourceMap (\r
+ IN PCI_IO_DEVICE *Bridge,\r
+ IN OUT PCI_RESOURCE_NODE *IoNode,\r
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem64Node\r
+ )\r
{\r
PCI_IO_DEVICE *Temp;\r
PCI_RESOURCE_NODE *IoBridge;\r
\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
\r
- while (CurrentLink && CurrentLink != &Bridge->ChildList) {\r
+ while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
\r
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
\r
// Note: For PPB, memory aperture is aligned with 1MB and IO aperture\r
// is aligned with 4KB\r
// This device is typically a bridge device like PPB and P2C\r
+ // Note: 0x1000 aligned\r
//\r
IoBridge = CreateResourceNode (\r
- Temp,\r
- 0,\r
- 0xFFF,\r
- PPB_IO_RANGE,\r
- PciBarTypeIo16,\r
- PciResUsageTypical\r
- ); //0x1000 aligned\r
- \r
+ Temp,\r
+ 0,\r
+ 0xFFF,\r
+ PPB_IO_RANGE,\r
+ PciBarTypeIo16,\r
+ PciResUsageTypical\r
+ );\r
+\r
Mem32Bridge = CreateResourceNode (\r
Temp,\r
0,\r
);\r
\r
PMem32Bridge = CreateResourceNode (\r
- Temp,\r
- 0,\r
- 0xFFFFF,\r
- PPB_PMEM32_RANGE,\r
- PciBarTypePMem32,\r
- PciResUsageTypical\r
- );\r
+ Temp,\r
+ 0,\r
+ 0xFFFFF,\r
+ PPB_PMEM32_RANGE,\r
+ PciBarTypePMem32,\r
+ PciResUsageTypical\r
+ );\r
\r
Mem64Bridge = CreateResourceNode (\r
Temp,\r
);\r
\r
PMem64Bridge = CreateResourceNode (\r
- Temp,\r
- 0,\r
- 0xFFFFF,\r
- PPB_PMEM64_RANGE,\r
- PciBarTypePMem64,\r
- PciResUsageTypical\r
- );\r
+ Temp,\r
+ 0,\r
+ 0xFFFFF,\r
+ PPB_PMEM64_RANGE,\r
+ PciBarTypePMem64,\r
+ PciResUsageTypical\r
+ );\r
\r
//\r
// Recursively create resouce map on this bridge\r
IoBridge\r
);\r
} else {\r
- gBS->FreePool (IoBridge);\r
+ FreePool (IoBridge);\r
IoBridge = NULL;\r
}\r
\r
Mem32Bridge\r
);\r
} else {\r
- gBS->FreePool (Mem32Bridge);\r
+ FreePool (Mem32Bridge);\r
Mem32Bridge = NULL;\r
}\r
\r
PMem32Bridge\r
);\r
} else {\r
- gBS->FreePool (PMem32Bridge);\r
+ FreePool (PMem32Bridge);\r
PMem32Bridge = NULL;\r
}\r
\r
Mem64Bridge\r
);\r
} else {\r
- gBS->FreePool (Mem64Bridge);\r
+ FreePool (Mem64Bridge);\r
Mem64Bridge = NULL;\r
}\r
\r
PMem64Bridge\r
);\r
} else {\r
- gBS->FreePool (PMem64Bridge);\r
+ FreePool (PMem64Bridge);\r
PMem64Bridge = NULL;\r
}\r
\r
//\r
// If it is P2C, apply hard coded resource padding\r
//\r
- //\r
if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {\r
ResourcePaddingForCardBusBridge (\r
Temp,\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
- //\r
+\r
//\r
// To do some platform specific resource padding ...\r
//\r
CalculateResourceAperture (Mem64Node);\r
CalculateResourceAperture (PMem64Node);\r
CalculateResourceAperture (IoNode);\r
+}\r
\r
- return EFI_SUCCESS;\r
+/**\r
+ This function is used to do the resource padding for a specific platform.\r
\r
-}\r
+ @param PciDev Pci device instance.\r
+ @param IoNode Resource info node for IO.\r
+ @param Mem32Node Resource info node for 32-bit memory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
+ @param Mem64Node Resource info node for 64-bit memory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
-EFI_STATUS\r
+**/\r
+VOID\r
ResourcePaddingPolicy (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function is used to do the resource padding for a specific platform\r
-\r
-Arguments:\r
-\r
- PciDev - A pointer to the PCI_IO_DEVICE structrue. \r
- IoNode - A pointer to the PCI_RESOURCE_NODE structrue.\r
- Mem32Node - A pointer to the PCI_RESOURCE_NODE structrue.\r
- PMem32Node - A pointer to the PCI_RESOURCE_NODE structrue.\r
- Mem64Node - A pointer to the PCI_RESOURCE_NODE structrue.\r
- PMem64Node - A pointer to the PCI_RESOURCE_NODE structrue.\r
-\r
-Returns:\r
- Status code\r
-\r
- None\r
-\r
---*/\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
//\r
// Create padding resource node\r
PMem64Node\r
);\r
}\r
+}\r
\r
- return EFI_SUCCESS;\r
+/**\r
+ This function is used to degrade resource if the upstream bridge\r
+ doesn't support certain resource. Degradation path is\r
+ PMEM64 -> MEM64 -> MEM32\r
+ PMEM64 -> PMEM32 -> MEM32\r
+ IO32 -> IO16.\r
\r
-}\r
+ @param Bridge Pci device instance.\r
+ @param Mem32Node Resource info node for 32-bit memory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
+ @param Mem64Node Resource info node for 64-bit memory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
-EFI_STATUS\r
+**/\r
+VOID\r
DegradeResource (\r
IN PCI_IO_DEVICE *Bridge,\r
IN PCI_RESOURCE_NODE *Mem32Node,\r
IN PCI_RESOURCE_NODE *Mem64Node,\r
IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function is used to degrade resource if the upstream bridge \r
- doesn't support certain resource. Degradation path is \r
- PMEM64 -> MEM64 -> MEM32\r
- PMEM64 -> PMEM32 -> MEM32\r
- IO32 -> IO16\r
-\r
-Arguments:\r
-\r
-Returns:\r
+{\r
+ BOOLEAN HasOprom;\r
+ PCI_IO_DEVICE *Temp;\r
+ LIST_ENTRY *CurrentLink;\r
\r
- None\r
+ //\r
+ // For RootBridge, PPB , P2C, go recursively to traverse all its children\r
+ // to find if this bridge and downstream has OptionRom.\r
+ //\r
+ HasOprom = FALSE;\r
+ CurrentLink = Bridge->ChildList.ForwardLink;\r
+ while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {\r
\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: Mem32Node - add argument and description to function comment\r
-// TODO: PMem32Node - add argument and description to function comment\r
-// TODO: Mem64Node - add argument and description to function comment\r
-// TODO: PMem64Node - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
+ Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);\r
+ if (Temp->RomSize != 0) {\r
+ HasOprom = TRUE;\r
+ break;\r
+ }\r
+ CurrentLink = CurrentLink->ForwardLink;\r
+ }\r
\r
//\r
// If bridge doesn't support Prefetchable\r
);\r
} else {\r
//\r
- // if no PMem32 request, still keep PMem64. Otherwise degrade to PMem32\r
+ // if no PMem32 request and no OptionRom request, still keep PMem64. Otherwise degrade to PMem32\r
//\r
- if (PMem32Node != NULL && PMem32Node->Length != 0 && Bridge->Parent != NULL ) { \r
+ if ((PMem32Node != NULL && (PMem32Node->Length != 0 && Bridge->Parent != NULL)) || HasOprom) {\r
//\r
// Fixed the issue that there is no resource for 64-bit (above 4G)\r
//\r
FALSE\r
);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
+/**\r
+ Test whether bridge device support decode resource.\r
+\r
+ @param Bridge Bridge device instance.\r
+ @param Decode Decode type according to resource type.\r
+\r
+ @return TRUE The bridge device support decode resource.\r
+ @return FALSE The bridge device don't support decode resource.\r
+\r
+**/\r
BOOLEAN\r
BridgeSupportResourceDecode (\r
IN PCI_IO_DEVICE *Bridge,\r
IN UINT32 Decode\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- TODO: Add function description\r
-\r
-Arguments:\r
-\r
- Bridge - TODO: add argument description\r
- Decode - TODO: add argument description\r
-\r
-Returns:\r
-\r
- TODO: add return values\r
-\r
---*/\r
{\r
- /*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
- \r
- None\r
-\r
---*/\r
- if ((Bridge->Decodes) & Decode) {\r
+ if (((Bridge->Decodes) & Decode) != 0) {\r
return TRUE;\r
}\r
\r
return FALSE;\r
}\r
\r
+/**\r
+ This function is used to program the resource allocated\r
+ for each resource node under specified bridge.\r
+\r
+ @param Base Base address of resource to be progammed.\r
+ @param Bridge PCI resource node for the bridge device.\r
+\r
+ @retval EFI_SUCCESS Successfully to program all resouces\r
+ on given PCI bridge device.\r
+ @retval EFI_OUT_OF_RESOURCES Base is all one.\r
+\r
+**/\r
EFI_STATUS\r
ProgramResource (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Bridge\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- This function is used to program the resource allocated \r
- for each resource node\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Base - add argument and description to function comment\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
LIST_ENTRY *CurrentLink;\r
PCI_RESOURCE_NODE *Node;\r
if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci))) {\r
\r
if (IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
+ //\r
+ // Program the PCI Card Bus device\r
+ //\r
ProgramP2C (Base, Node);\r
} else {\r
+ //\r
+ // Program the PCI device BAR\r
+ //\r
ProgramBar (Base, Node);\r
}\r
} else {\r
+ //\r
+ // Program the PCI devices under this bridge\r
+ //\r
Status = ProgramResource (Base + Node->Offset, Node);\r
-\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
+/**\r
+ Program Bar register for PCI device.\r
+\r
+ @param Base Base address for PCI device resource to be progammed.\r
+ @param Node Point to resoure node structure.\r
+\r
+**/\r
+VOID\r
ProgramBar (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
- \r
- None\r
-\r
---*/\r
-// TODO: Base - add argument and description to function comment\r
-// TODO: Node - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT64 Address;\r
//\r
Node->PciDev->Allocated = TRUE;\r
\r
+ ASSERT (Node->Bar < PCI_MAX_BAR);\r
switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {\r
\r
case PciBarTypeIo16:\r
case PciBarTypeMem32:\r
case PciBarTypePMem32:\r
\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
\r
\r
Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);\r
\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) RShiftU64 (Address, 32);\r
\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
\r
default:\r
break;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
+/**\r
+ Program PCI-PCI bridge apperture.\r
+\r
+ @param Base Base address for resource.\r
+ @param Node Point to resoure node structure.\r
+\r
+**/\r
+VOID\r
ProgramPpbApperture (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
- \r
- None\r
-\r
---*/\r
-// TODO: Base - add argument and description to function comment\r
-// TODO: Node - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT64 Address;\r
\r
Address = 0;\r
//\r
- // if no device south of this PPB, return anyway\r
+ // If no device resource of this PPB, return anyway\r
// Apperture is set default in the initialization code\r
//\r
if (Node->Length == 0 || Node->ResourceUsage == PciResUsagePadding) {\r
//\r
// For padding resource node, just ignore when programming\r
//\r
- return EFI_SUCCESS;\r
+ return ;\r
}\r
\r
PciIo = &(Node->PciDev->PciIo);\r
\r
case PPB_BAR_0:\r
case PPB_BAR_1:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
case PPB_IO_RANGE:\r
\r
Address32 = ((UINT32) (Address)) >> 8;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- 0x1C,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ 0x1C,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 >>= 8;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x30,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x30,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) (Address + Node->Length - 1);\r
Address32 = ((UINT32) (Address32)) >> 8;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- 0x1D,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ 0x1D,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 >>= 8;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x32,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x32,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
case PPB_MEM32_RANGE:\r
\r
Address32 = ((UINT32) (Address)) >> 16;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x20,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x20,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) (Address + Node->Length - 1);\r
Address32 = ((UINT32) (Address32)) >> 16;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x22,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x22,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
case PPB_PMEM64_RANGE:\r
\r
Address32 = ((UINT32) (Address)) >> 16;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x24,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x24,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) (Address + Node->Length - 1);\r
Address32 = ((UINT32) (Address32)) >> 16;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x26,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x26,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) RShiftU64 (Address, 32);\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x28,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ 0x28,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x2C,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ 0x2C,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
default:\r
break;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
+/**\r
+ Program parent bridge for Option Rom.\r
+\r
+ @param PciDevice Pci deivce instance.\r
+ @param OptionRomBase Base address for Optiona Rom.\r
+ @param Enable Enable or disable PCI memory.\r
+\r
+**/\r
+VOID\r
ProgrameUpstreamBridgeForRom (\r
IN PCI_IO_DEVICE *PciDevice,\r
IN UINT32 OptionRomBase,\r
IN BOOLEAN Enable\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
---*/\r
-// TODO: PciDevice - add argument and description to function comment\r
-// TODO: OptionRomBase - add argument and description to function comment\r
-// TODO: Enable - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
PCI_IO_DEVICE *Parent;\r
PCI_RESOURCE_NODE Node;\r
//\r
Parent = PciDevice->Parent;\r
ZeroMem (&Node, sizeof (Node));\r
- while (Parent) {\r
+ while (Parent != NULL) {\r
if (!IS_PCI_BRIDGE (&Parent->Pci)) {\r
break;\r
}\r
Node.Offset = 0;\r
\r
//\r
- // Program PPB to only open a single <= 16<MB apperture\r
+ // Program PPB to only open a single <= 16MB apperture\r
//\r
if (Enable) {\r
ProgramPpbApperture (OptionRomBase, &Node);\r
- PciEnableCommandRegister (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
+ PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
} else {\r
InitializePpb (Parent);\r
- PciDisableCommandRegister (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
+ PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);\r
}\r
\r
Parent = Parent->Parent;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-BOOLEAN\r
-ResourceRequestExisted (\r
- IN PCI_RESOURCE_NODE *Bridge\r
- )\r
-/*++\r
-\r
-Routine Description:\r
+/**\r
+ Test whether resource exists for a bridge.\r
\r
-Arguments:\r
+ @param Bridge Point to resource node for a bridge.\r
\r
- Bridge - A pointer to the PCI_RESOURCE_NODE.\r
+ @retval TRUE There is resource on the given bridge.\r
+ @retval FALSE There isn't resource on the given bridge.\r
\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
+**/\r
+BOOLEAN\r
+ResourceRequestExisted (\r
+ IN PCI_RESOURCE_NODE *Bridge\r
+ )\r
{\r
if (Bridge != NULL) {\r
if (!IsListEmpty (&Bridge->ChildList) || Bridge->Length != 0) {\r
return FALSE;\r
}\r
\r
-EFI_STATUS\r
-InitializeResourcePool (\r
- PCI_RESOURCE_NODE *ResourcePool,\r
- PCI_BAR_TYPE ResourceType\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
+/**\r
+ Initialize resource pool structure.\r
\r
- None\r
+ @param ResourcePool Point to resource pool structure. This pool\r
+ is reset to all zero when returned.\r
+ @param ResourceType Type of resource.\r
\r
---*/\r
-// TODO: ResourcePool - add argument and description to function comment\r
-// TODO: ResourceType - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+InitializeResourcePool (\r
+ IN OUT PCI_RESOURCE_NODE *ResourcePool,\r
+ IN PCI_BAR_TYPE ResourceType\r
+ )\r
{\r
-\r
ZeroMem (ResourcePool, sizeof (PCI_RESOURCE_NODE));\r
ResourcePool->ResType = ResourceType;\r
ResourcePool->Signature = PCI_RESOURCE_SIGNATURE;\r
InitializeListHead (&ResourcePool->ChildList);\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-GetResourceMap (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE **IoBridge,\r
- PCI_RESOURCE_NODE **Mem32Bridge,\r
- PCI_RESOURCE_NODE **PMem32Bridge,\r
- PCI_RESOURCE_NODE **Mem64Bridge,\r
- PCI_RESOURCE_NODE **PMem64Bridge,\r
- PCI_RESOURCE_NODE *IoPool,\r
- PCI_RESOURCE_NODE *Mem32Pool,\r
- PCI_RESOURCE_NODE *PMem32Pool,\r
- PCI_RESOURCE_NODE *Mem64Pool,\r
- PCI_RESOURCE_NODE *PMem64Pool\r
- )\r
-/*++\r
\r
-Routine Description:\r
+/**\r
+ Get all resource information for given Pci device.\r
\r
-Arguments:\r
+ @param PciDev Pci device instance.\r
+ @param IoBridge Io resource node.\r
+ @param Mem32Bridge 32-bit memory node.\r
+ @param PMem32Bridge 32-bit Pmemory node.\r
+ @param Mem64Bridge 64-bit memory node.\r
+ @param PMem64Bridge 64-bit PMemory node.\r
+ @param IoPool Link list header for Io resource.\r
+ @param Mem32Pool Link list header for 32-bit memory.\r
+ @param PMem32Pool Link list header for 32-bit Prefetchable memory.\r
+ @param Mem64Pool Link list header for 64-bit memory.\r
+ @param PMem64Pool Link list header for 64-bit Prefetchable memory.\r
\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: PciDev - add argument and description to function comment\r
-// TODO: IoBridge - add argument and description to function comment\r
-// TODO: Mem32Bridge - add argument and description to function comment\r
-// TODO: PMem32Bridge - add argument and description to function comment\r
-// TODO: Mem64Bridge - add argument and description to function comment\r
-// TODO: PMem64Bridge - add argument and description to function comment\r
-// TODO: IoPool - add argument and description to function comment\r
-// TODO: Mem32Pool - add argument and description to function comment\r
-// TODO: PMem32Pool - add argument and description to function comment\r
-// TODO: Mem64Pool - add argument and description to function comment\r
-// TODO: PMem64Pool - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+GetResourceMap (\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE **IoBridge,\r
+ IN PCI_RESOURCE_NODE **Mem32Bridge,\r
+ IN PCI_RESOURCE_NODE **PMem32Bridge,\r
+ IN PCI_RESOURCE_NODE **Mem64Bridge,\r
+ IN PCI_RESOURCE_NODE **PMem64Bridge,\r
+ IN PCI_RESOURCE_NODE *IoPool,\r
+ IN PCI_RESOURCE_NODE *Mem32Pool,\r
+ IN PCI_RESOURCE_NODE *PMem32Pool,\r
+ IN PCI_RESOURCE_NODE *Mem64Pool,\r
+ IN PCI_RESOURCE_NODE *PMem64Pool\r
+ )\r
{\r
\r
PCI_RESOURCE_NODE *Temp;\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
+/**\r
+ Destory given resource tree.\r
+\r
+ @param Bridge PCI resource root node of resource tree.\r
+\r
+**/\r
+VOID\r
DestroyResourceTree (\r
IN PCI_RESOURCE_NODE *Bridge\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
PCI_RESOURCE_NODE *Temp;\r
LIST_ENTRY *CurrentLink;\r
CurrentLink = Bridge->ChildList.ForwardLink;\r
\r
Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);\r
+ ASSERT (Temp);\r
\r
RemoveEntryList (CurrentLink);\r
\r
DestroyResourceTree (Temp);\r
}\r
\r
- gBS->FreePool (Temp);\r
+ FreePool (Temp);\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-RecordReservedResource (\r
- IN UINT64 Base,\r
- IN UINT64 Length,\r
- IN PCI_BAR_TYPE ResType,\r
- IN PCI_IO_DEVICE *Bridge\r
- )\r
-/*++\r
-\r
-Routine Description:\r
- \r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
+/**\r
+ Insert resource padding for P2C.\r
\r
---*/\r
-// TODO: Base - add argument and description to function comment\r
-// TODO: Length - add argument and description to function comment\r
-// TODO: ResType - add argument and description to function comment\r
-// TODO: Bridge - add argument and description to function comment\r
-// TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
-{\r
- PCI_RESERVED_RESOURCE_LIST *ReservedNode;\r
-\r
- ReservedNode = AllocatePool (sizeof (PCI_RESERVED_RESOURCE_LIST));\r
- if (ReservedNode == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- ReservedNode->Signature = RESERVED_RESOURCE_SIGNATURE;\r
- ReservedNode->Node.Base = Base;\r
- ReservedNode->Node.Length = Length;\r
- ReservedNode->Node.ResType = ResType;\r
-\r
- InsertTailList (&Bridge->ReservedResourceList, &(ReservedNode->Link));\r
-\r
- return EFI_SUCCESS;\r
-}\r
+ @param PciDev Pci device instance.\r
+ @param IoNode Resource info node for IO.\r
+ @param Mem32Node Resource info node for 32-bit memory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
+ @param Mem64Node Resource info node for 64-bit memory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
-EFI_STATUS\r
+**/\r
+VOID\r
ResourcePaddingForCardBusBridge (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
-// TODO: PciDev - add argument and description to function comment\r
-// TODO: IoNode - add argument and description to function comment\r
-// TODO: Mem32Node - add argument and description to function comment\r
-// TODO: PMem32Node - add argument and description to function comment\r
-// TODO: Mem64Node - add argument and description to function comment\r
-// TODO: PMem64Node - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
PCI_RESOURCE_NODE *Node;\r
\r
// Bar 1 denodes memory range 0\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x2000000,\r
- 0x1ffffff,\r
- 1,\r
- PciBarTypeMem32,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x2000000,\r
+ 0x1ffffff,\r
+ 1,\r
+ PciBarTypeMem32,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
Mem32Node,\r
// Bar 2 denodes memory range1\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x2000000,\r
- 0x1ffffff,\r
- 2,\r
- PciBarTypePMem32,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x2000000,\r
+ 0x1ffffff,\r
+ 2,\r
+ PciBarTypePMem32,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
PMem32Node,\r
// Bar 3 denodes io range 0\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x100,\r
- 0xff,\r
- 3,\r
- PciBarTypeIo16,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x100,\r
+ 0xff,\r
+ 3,\r
+ PciBarTypeIo16,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
IoNode,\r
// Bar 4 denodes io range 0\r
//\r
Node = CreateResourceNode (\r
- PciDev,\r
- 0x100,\r
- 0xff,\r
- 4,\r
- PciBarTypeIo16,\r
- PciResUsagePadding\r
- );\r
+ PciDev,\r
+ 0x100,\r
+ 0xff,\r
+ 4,\r
+ PciBarTypeIo16,\r
+ PciResUsagePadding\r
+ );\r
\r
InsertResourceNode (\r
IoNode,\r
Node\r
);\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
+/**\r
+ Program PCI Card device register for given resource node.\r
+\r
+ @param Base Base address of PCI Card device to be programmed.\r
+ @param Node Given resource node.\r
+\r
+**/\r
+VOID\r
ProgramP2C (\r
IN UINT64 Base,\r
IN PCI_RESOURCE_NODE *Node\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
-\r
-Returns:\r
- \r
- None\r
-\r
---*/\r
-// TODO: Base - add argument and description to function comment\r
-// TODO: Node - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
{\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT64 Address;\r
switch (Node->Bar) {\r
\r
case P2C_BAR_0:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
break;\r
\r
case P2C_MEM_1:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x1c,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_0,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x20,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_LIMIT_0,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
if (Node->ResType == PciBarTypeMem32) {\r
-\r
//\r
// Set non-prefetchable bit\r
//\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl &= 0xfeff;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
\r
} else {\r
-\r
//\r
// Set pre-fetchable bit\r
//\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl |= 0x0100;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
}\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
break;\r
\r
case P2C_MEM_2:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x24,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_1,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x28,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_LIMIT_1,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
if (Node->ResType == PciBarTypeMem32) {\r
\r
//\r
// Set non-prefetchable bit\r
//\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl &= 0xfdff;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
} else {\r
\r
//\r
// Set pre-fetchable bit\r
//\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
-\r
- BridgeControl |= 0x0200;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x3e,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
+\r
+ BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
}\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
break;\r
\r
case P2C_IO_1:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x2c,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_0_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
+\r
TempAddress = Address + Node->Length - 1;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x30,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_LIMIT_0_LOWER,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
break;\r
\r
case P2C_IO_2:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x34,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_1_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x38,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_LIMIT_1_LOWER,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
default:\r
break;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-EFI_STATUS\r
-ApplyResourcePadding (\r
- PCI_IO_DEVICE *PciDev,\r
- PCI_RESOURCE_NODE *IoNode,\r
- PCI_RESOURCE_NODE *Mem32Node,\r
- PCI_RESOURCE_NODE *PMem32Node,\r
- PCI_RESOURCE_NODE *Mem64Node,\r
- PCI_RESOURCE_NODE *PMem64Node\r
- )\r
-/*++\r
-\r
-Routine Description:\r
-\r
-Arguments:\r
+/**\r
+ Create padding resource node.\r
\r
-Returns:\r
- \r
- None\r
+ @param PciDev Pci device instance.\r
+ @param IoNode Resource info node for IO.\r
+ @param Mem32Node Resource info node for 32-bit memory.\r
+ @param PMem32Node Resource info node for 32-bit Prefetchable Memory.\r
+ @param Mem64Node Resource info node for 64-bit memory.\r
+ @param PMem64Node Resource info node for 64-bit Prefetchable Memory.\r
\r
---*/\r
-// TODO: PciDev - add argument and description to function comment\r
-// TODO: IoNode - add argument and description to function comment\r
-// TODO: Mem32Node - add argument and description to function comment\r
-// TODO: PMem32Node - add argument and description to function comment\r
-// TODO: Mem64Node - add argument and description to function comment\r
-// TODO: PMem64Node - add argument and description to function comment\r
-// TODO: EFI_SUCCESS - add return value to function comment\r
+**/\r
+VOID\r
+ApplyResourcePadding (\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN PCI_RESOURCE_NODE *IoNode,\r
+ IN PCI_RESOURCE_NODE *Mem32Node,\r
+ IN PCI_RESOURCE_NODE *PMem32Node,\r
+ IN PCI_RESOURCE_NODE *Mem64Node,\r
+ IN PCI_RESOURCE_NODE *PMem64Node\r
+ )\r
{\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
PCI_RESOURCE_NODE *Node;\r
// prefechable\r
//\r
if (Ptr->SpecificFlag == 0x6) {\r
- if (Ptr->AddrLen) {\r
+ if (Ptr->AddrLen != 0) {\r
Node = CreateResourceNode (\r
PciDev,\r
Ptr->AddrLen,\r
// Non-prefechable\r
//\r
if (Ptr->SpecificFlag == 0) {\r
- if (Ptr->AddrLen) {\r
+ if (Ptr->AddrLen != 0) {\r
Node = CreateResourceNode (\r
PciDev,\r
Ptr->AddrLen,\r
// prefechable\r
//\r
if (Ptr->SpecificFlag == 0x6) {\r
- if (Ptr->AddrLen) {\r
+ if (Ptr->AddrLen != 0) {\r
Node = CreateResourceNode (\r
PciDev,\r
Ptr->AddrLen,\r
// Non-prefechable\r
//\r
if (Ptr->SpecificFlag == 0) {\r
- if (Ptr->AddrLen) {\r
+ if (Ptr->AddrLen != 0) {\r
Node = CreateResourceNode (\r
PciDev,\r
Ptr->AddrLen,\r
\r
Ptr++;\r
}\r
-\r
- return EFI_SUCCESS;\r
}\r
\r
-//\r
-// Light PCI bus driver woundn't support hotplug root device\r
-// So no need to pad resource for them\r
-//\r
+/**\r
+ Get padding resource for PCI-PCI bridge.\r
+\r
+ @param PciIoDevice PCI-PCI bridge device instance.\r
+\r
+ @note Feature flag PcdPciBusHotplugDeviceSupport determines\r
+ whether need to pad resource for them.\r
+**/\r
VOID\r
GetResourcePaddingPpb (\r
IN PCI_IO_DEVICE *PciIoDevice\r
)\r
-/*++\r
-\r
-Routine Description:\r
-\r
- Get resource.\r
-\r
-Arguments:\r
-\r
- PciIoDevice A pointer to a pci device.\r
-\r
-Returns:\r
-\r
- None\r
-\r
---*/\r
{\r
- if (gPciHotPlugInit) {\r
+ if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
if (PciIoDevice->ResourcePaddingDescriptors == NULL) {\r
GetResourcePaddingForHpb (PciIoDevice);\r
}\r
}\r
}\r
+\r
projects / mirror_edk2.git / blobdiff