#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/PcdLib.h>\r
-#include <Library/PciIncompatibleDeviceSupportLib.h>\r
#include <Library/PeCoffLib.h>\r
\r
#include <IndustryStandard/Pci.h>\r
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
\r
[LibraryClasses]\r
- PciIncompatibleDeviceSupportLib\r
PcdLib\r
DevicePathLib\r
UefiBootServicesTableLib\r
[FeaturePcd.common]\r
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport\r
\r
-[Pcd.common]\r
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask\r
-\r
# [Event]\r
# ##\r
# # Notify event set by CreateEventForHpc () for PCI Hot Plug controller.\r
PciIo = &PciIoDevice->PciIo;\r
\r
if (Operation != EFI_SET_REGISTER) {\r
- Status = PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- Offset,\r
- 1,\r
- &OldCommand\r
- );\r
+ Status = PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ Offset,\r
+ 1,\r
+ &OldCommand\r
+ );\r
\r
if (Operation == EFI_GET_REGISTER) {\r
*PtrCommand = OldCommand;\r
OldCommand = Command;\r
}\r
\r
- return PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- Offset,\r
- 1,\r
- &OldCommand\r
- );\r
+ return PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ Offset,\r
+ 1,\r
+ &OldCommand\r
+ );\r
}\r
\r
/**\r
CapabilityPtr = 0;\r
if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {\r
\r
- PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint8,\r
- EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r
- 1,\r
- &CapabilityPtr\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint8,\r
+ EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,\r
+ 1,\r
+ &CapabilityPtr\r
+ );\r
} else {\r
\r
- PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint8,\r
- PCI_CAPBILITY_POINTER_OFFSET,\r
- 1,\r
- &CapabilityPtr\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint8,\r
+ PCI_CAPBILITY_POINTER_OFFSET,\r
+ 1,\r
+ &CapabilityPtr\r
+ );\r
}\r
}\r
\r
while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {\r
- PciIoRead (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint16,\r
- CapabilityPtr,\r
- 1,\r
- &CapabilityEntry\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint16,\r
+ CapabilityPtr,\r
+ 1,\r
+ &CapabilityEntry\r
+ );\r
\r
CapabilityID = (UINT8) CapabilityEntry;\r
\r
//\r
PciIo = &(PciIoDevice->PciIo);\r
Data8 = PCI_INT_LINE_UNKNOWN;\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);\r
\r
//\r
// Process OpRom\r
\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint16,\r
Address,\r
1,\r
// Initialize SubBusNumber to SecondBus\r
//\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint8,\r
Address,\r
1,\r
if (IS_PCI_BRIDGE (&Pci)) {\r
\r
Register8 = 0xFF;\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint8,\r
Address,\r
1,\r
//\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);\r
\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint8,\r
Address,\r
1,\r
// If there is at least one type of resource request,\r
// allocate a acpi resource node\r
//\r
- Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
if (Configuration == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- ZeroMem (\r
- Configuration,\r
- sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
- );\r
-\r
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
\r
//\r
//\r
// If there is no resource request\r
//\r
- Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
if (Configuration == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- ZeroMem (Configuration, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
-\r
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);\r
Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
\r
SubBusNumber = 0;\r
StartBusNumber = 0;\r
PciIo = &(BridgeDev->PciIo);\r
- Status = PciIoRead (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);\r
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
//\r
// Read the Vendor ID register\r
//\r
- Status = PciRootBridgeIoRead (\r
- PciRootBridgeIo,\r
- NULL,\r
- EfiPciWidthUint32,\r
- Address,\r
- 1,\r
- Pci\r
- );\r
+ Status = PciRootBridgeIo->Pci.Read (\r
+ PciRootBridgeIo,\r
+ EfiPciWidthUint32,\r
+ Address,\r
+ 1,\r
+ Pci\r
+ );\r
\r
if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) {\r
//\r
// Read the entire config header for the device\r
//\r
- Status = PciRootBridgeIoRead (\r
- PciRootBridgeIo,\r
- NULL,\r
- EfiPciWidthUint32,\r
- Address,\r
- sizeof (PCI_TYPE00) / sizeof (UINT32),\r
- Pci\r
- );\r
+ Status = PciRootBridgeIo->Pci.Read (\r
+ PciRootBridgeIo,\r
+ EfiPciWidthUint32,\r
+ Address,\r
+ sizeof (PCI_TYPE00) / sizeof (UINT32),\r
+ Pci\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
//\r
PciIo = &(PciIoDevice->PciIo);\r
\r
- Status = PciIoRead (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);\r
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET, 1, &SecBus);\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
//\r
// Test whether it support 32 decode or not\r
//\r
- PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
- PciIoRead (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);\r
\r
if (Value != 0) {\r
if ((Value & 0x01) != 0) {\r
//\r
// Preserve the original value\r
//\r
- PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
\r
//\r
// Raise TPL to high level to disable timer interrupt while the BAR is probed\r
//\r
OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);\r
- PciIoRead (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne);\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &Value);\r
\r
//\r
// Write back the original value\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue);\r
\r
//\r
// Restore TPL to its original level\r
// Read the status register\r
//\r
PciIo = &PciIoDevice->PciIo;\r
- Status = PciIoRead (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);\r
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, StatusIndex, 1, &StatusRegister);\r
if (EFI_ERROR (Status)) {\r
return EFI_UNSUPPORTED;\r
}\r
/**\r
This routine is used to update the bar information for those incompatible PCI device.\r
\r
- @param PciIoDevice Pci device instance.\r
+ @param PciIoDevice Input Pci device instance. Output Pci device instance with updated\r
+ Bar information.\r
\r
@retval EFI_SUCCESS Successfully updated bar information.\r
@retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.\r
- @retval other Failed to check incompatibility device.\r
\r
**/\r
EFI_STATUS\r
UpdatePciInfo (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN OUT PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
EFI_STATUS Status;\r
UINTN BarIndex;\r
UINTN BarEndIndex;\r
BOOLEAN SetFlag;\r
- EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
VOID *Configuration;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r
\r
\r
}\r
\r
- if (EFI_ERROR (Status)) {\r
- //\r
- // Check whether the device belongs to incompatible devices from library or not\r
- // If it is , then get its special requirement in the ACPI table\r
- //\r
- if (PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT) {\r
- PciDeviceInfo.VendorID = PciIoDevice->Pci.Hdr.VendorId;\r
- PciDeviceInfo.DeviceID = PciIoDevice->Pci.Hdr.DeviceId;\r
- PciDeviceInfo.RevisionID = PciIoDevice->Pci.Hdr.RevisionID;\r
- PciDeviceInfo.SubsystemVendorID = PciIoDevice->Pci.Device.SubsystemVendorID;\r
- PciDeviceInfo.SubsystemID = PciIoDevice->Pci.Device.SubsystemID;\r
-\r
- Status = PciResourceUpdateCheck (&PciDeviceInfo, &Configuration);\r
- }\r
- }\r
-\r
if (EFI_ERROR (Status) || Configuration == NULL ) {\r
return EFI_UNSUPPORTED;\r
}\r
Ptr++;\r
}\r
\r
- if (Configuration != NULL) {\r
- FreePool (Configuration);\r
- }\r
+ FreePool (Configuration);\r
\r
return EFI_SUCCESS;\r
}\r
/**\r
This routine will update the alignment with the new alignment.\r
\r
- @param Alignment Old alignment.\r
+ @param Alignment Input Old alignment. Output updated alignment.\r
@param NewAlignment New alignment.\r
\r
**/\r
VOID\r
SetNewAlign (\r
- IN UINT64 *Alignment,\r
- IN UINT64 NewAlignment\r
+ IN OUT UINT64 *Alignment,\r
+ IN UINT64 NewAlignment\r
)\r
{\r
UINT64 OldAlignment;\r
Value = 0;\r
\r
Status = BarExisted (\r
- PciIoDevice,\r
- Offset,\r
- &Value,\r
- &OriginalValue\r
- );\r
+ PciIoDevice,\r
+ Offset,\r
+ &Value,\r
+ &OriginalValue\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
PciIoDevice->PciBar[BarIndex].BaseAddress = 0;\r
Offset += 4;\r
\r
Status = BarExisted (\r
- PciIoDevice,\r
- Offset,\r
- &Value,\r
- &OriginalValue\r
- );\r
+ PciIoDevice,\r
+ Offset,\r
+ &Value,\r
+ &OriginalValue\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
return Offset + 4;\r
// has not been alloacted\r
//\r
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);\r
}\r
}\r
\r
// Io32, pMem32, pMem64 to quiescent state\r
// Resource base all ones, Resource limit all zeros\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2C, 1, &gAllZero);\r
\r
//\r
- // don't support use io32 as for now\r
+ // Don't support use io32 as for now\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x30, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x32, 1, &gAllZero);\r
\r
//\r
// Force Interrupt line to zero for cards that come up randomly\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
}\r
\r
/**\r
// Io32, pMem32, pMem64 to quiescent state(\r
// Resource base all ones, Resource limit all zeros\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x1c, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x20, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x24, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x28, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x2c, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x30, 1, &gAllZero);\r
\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x34, 1, &gAllOne);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, 0x38, 1, &gAllZero);\r
\r
//\r
// Force Interrupt line to zero for cards that come up randomly\r
//\r
- PciIoWrite (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &gAllZero);\r
}\r
\r
/**\r
RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;\r
\r
Status = PciPciDeviceInfoCollector (\r
- RootBridgeDev,\r
- (UINT8) MinBus\r
- );\r
+ RootBridgeDev,\r
+ (UINT8) MinBus\r
+ );\r
\r
if (!EFI_ERROR (Status)) {\r
\r
// Check to see whether a pci device is present\r
//\r
Status = PciDevicePresent (\r
- PciRootBridgeIo,\r
- &Pci,\r
- StartBusNumber,\r
- Device,\r
- Func\r
- );\r
+ PciRootBridgeIo,\r
+ &Pci,\r
+ StartBusNumber,\r
+ Device,\r
+ Func\r
+ );\r
\r
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci))) {\r
\r
Register = 0;\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);\r
- Status = PciRootBridgeIoRead (\r
- PciRootBridgeIo,\r
- &Pci,\r
- EfiPciWidthUint32,\r
- Address,\r
- 1,\r
- &Register\r
- );\r
+ Status = PciRootBridgeIo->Pci.Read (\r
+ PciRootBridgeIo,\r
+ EfiPciWidthUint32,\r
+ Address,\r
+ 1,\r
+ &Register\r
+ );\r
SecondaryBus = (UINT8)(Register >> 8);\r
\r
if (SecondaryBus != 0) {\r
// Reset register 18h, 19h, 1Ah on PCI Bridge\r
//\r
Register &= 0xFF000000;\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint32,\r
Address,\r
1,\r
/**\r
This routine is used to update the bar information for those incompatible PCI device.\r
\r
- @param PciIoDevice Pci device instance.\r
+ @param PciIoDevice Input Pci device instance. Output Pci device instance with updated\r
+ Bar information.\r
\r
@retval EFI_SUCCESS Successfully updated bar information.\r
@retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.\r
- @retval other Failed to check incompatibility device.\r
\r
**/\r
EFI_STATUS\r
UpdatePciInfo (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN OUT PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
This routine will update the alignment with the new alignment.\r
\r
- @param Alignment Old alignment.\r
+ @param Alignment Input Old alignment. Output updated alignment.\r
@param NewAlignment New alignment.\r
\r
**/\r
VOID\r
SetNewAlign (\r
- IN UINT64 *Alignment,\r
- IN UINT64 NewAlignment\r
+ IN OUT UINT64 *Alignment,\r
+ IN UINT64 NewAlignment\r
);\r
\r
/**\r
}\r
\r
Status = PciIoDevice->PciRootBridgeIo->Pci.Read (\r
- PciIoDevice->PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
- Address,\r
- Count,\r
- Buffer\r
- );\r
+ PciIoDevice->PciRootBridgeIo,\r
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);\r
NumConfig = 1;\r
}\r
\r
- Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
if (Configuration == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
- ZeroMem (\r
- Configuration,\r
- sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
- );\r
-\r
Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;\r
\r
if (NumConfig == 1) {\r
//\r
if (!gFullEnumeration) {\r
Address = 0;\r
- PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_MEMORY_BASE_0,\r
- 1,\r
- &Address\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &(PciIoDevice->PciIo),\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_0,\r
+ 1,\r
+ &Address\r
+ );\r
\r
(PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64) (Address);\r
(PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000;\r
(PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32;\r
\r
Address = 0;\r
- PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_MEMORY_BASE_1,\r
- 1,\r
- &Address\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &(PciIoDevice->PciIo),\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_1,\r
+ 1,\r
+ &Address\r
+ );\r
(PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64) (Address);\r
(PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000;\r
(PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;\r
\r
Address = 0;\r
- PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_IO_BASE_0_LOWER,\r
- 1,\r
- &Address\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &(PciIoDevice->PciIo),\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_0_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
(PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64) (Address);\r
(PciIoDevice->PciBar)[P2C_IO_1].Length = 0x100;\r
(PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16;\r
\r
Address = 0;\r
- PciIoRead (\r
- &(PciIoDevice->PciIo),\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_IO_BASE_1_LOWER,\r
- 1,\r
- &Address\r
- );\r
+ PciIoDevice->PciIo.Pci.Read (\r
+ &(PciIoDevice->PciIo),\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_1_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
(PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64) (Address);\r
(PciIoDevice->PciBar)[P2C_IO_2].Length = 0x100;\r
(PciIoDevice->PciBar)[P2C_IO_2].BarType = PciBarTypeIo16;\r
Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);\r
\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint16,\r
Address,\r
1,\r
//\r
Register = 0xFF;\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint8,\r
Address,\r
1,\r
//\r
Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &Pci,\r
EfiPciWidthUint8,\r
Address,\r
1,\r
**/\r
EFI_STATUS\r
PciHostBridgeEnumerator (\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
)\r
{\r
EFI_HANDLE RootBridgeHandle;\r
\r
return EFI_SUCCESS;\r
}\r
-\r
-/**\r
- Read PCI device configuration register by specified address.\r
-\r
- This function check the incompatiblilites on PCI device. Return the register\r
- value.\r
-\r
- @param PciRootBridgeIo PCI root bridge io protocol instance.\r
- @param PciIo PCI IO protocol instance.\r
- @param PciDeviceInfo PCI device information.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.\r
- @retval other Some error occurred when reading PCI device configuration space\r
- or checking incompatibility.\r
-\r
-**/\r
-EFI_STATUS\r
-ReadConfigData (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 Width,\r
- IN UINT64 Offset,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT64 AccessWidth;\r
- EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData;\r
- UINT64 AccessAddress;\r
- UINTN Stride;\r
- UINT64 TempBuffer;\r
- UINT8 *Pointer;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
- ASSERT (Buffer != NULL);\r
-\r
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {\r
- //\r
- // Check access compatibility at first time\r
- //\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, Offset & 0xff, Width, &PciRegisterAccessData);\r
-\r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // There exists incompatibility on this operation\r
- //\r
- AccessWidth = Width;\r
-\r
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {\r
- AccessWidth = PciRegisterAccessData->Width;\r
- }\r
-\r
- AccessAddress = Offset & ~((1 << AccessWidth) - 1);\r
-\r
- TempBuffer = 0;\r
- Stride = 0;\r
- Pointer = (UINT8 *) &TempBuffer;\r
-\r
- while (TRUE) {\r
-\r
- if (PciRootBridgeIo != NULL) {\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
- AccessAddress,\r
- 1,\r
- Pointer\r
- );\r
- } else if (PciIo != NULL) {\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
- (UINT32) AccessAddress,\r
- 1,\r
- Pointer\r
- );\r
- }\r
-\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- Stride = (UINTN)1 << AccessWidth;\r
- AccessAddress += Stride;\r
- if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {\r
- //\r
- // If all datas have been read, exit\r
- //\r
- break;\r
- }\r
-\r
- Pointer += Stride;\r
-\r
- if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {\r
- //\r
- // If current offset doesn't reach the end\r
- //\r
- continue;\r
- }\r
-\r
- //\r
- // Continue checking access incompatibility\r
- //\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_READ, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);\r
- if (Status == EFI_SUCCESS) {\r
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {\r
- AccessWidth = PciRegisterAccessData->Width;\r
- }\r
- }\r
- }\r
-\r
- switch (Width) {\r
- case EfiPciWidthUint8:\r
- * (UINT8 *) Buffer = (UINT8) TempBuffer;\r
- break;\r
- case EfiPciWidthUint16:\r
- * (UINT16 *) Buffer = (UINT16) TempBuffer;\r
- break;\r
- case EfiPciWidthUint32:\r
- * (UINT32 *) Buffer = (UINT32) TempBuffer;\r
- break;\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- return Status;\r
- }\r
- }\r
- //\r
- // AccessWidth incompatible check not supportted\r
- // or, there doesn't exist incompatibility on this operation\r
- //\r
- if (PciRootBridgeIo != NULL) {\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
- Offset,\r
- 1,\r
- Buffer\r
- );\r
-\r
- } else {\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
- (UINT32) Offset,\r
- 1,\r
- Buffer\r
- );\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- Update register value by checking PCI device incompatibility.\r
-\r
- This function check register value incompatibilites on PCI device. Return the register\r
- value.\r
-\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
- @param AccessType Access type, READ or WRITE.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space.\r
- @param Buffer Store the register data.\r
-\r
- @retval EFI_SUCCESS The data has been updated.\r
- @retval EFI_UNSUPPORTED Width is invalid for this PCI root bridge.\r
- @retval other Some error occurred when checking incompatibility.\r
-\r
-**/\r
-EFI_STATUS\r
-UpdateConfigData (\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 AccessType,\r
- IN UINT64 Width,\r
- IN UINT64 Offset,\r
- IN OUT VOID *Buffer\r
-)\r
-{\r
- EFI_STATUS Status;\r
- EFI_PCI_REGISTER_VALUE_DATA *PciRegisterData;\r
- UINT32 AndValue;\r
- UINT32 OrValue;\r
- UINT32 TempValue;\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Check register value incompatibility\r
- //\r
- Status = PciRegisterUpdateCheck (PciDeviceInfo, AccessType, Offset & 0xff, &PciRegisterData);\r
- if (Status == EFI_SUCCESS) {\r
-\r
- AndValue = ((UINT32) PciRegisterData->AndValue) >> (((UINT8) Offset & 0x3) * 8);\r
- OrValue = ((UINT32) PciRegisterData->OrValue) >> (((UINT8) Offset & 0x3) * 8);\r
-\r
- TempValue = * (UINT32 *) Buffer;\r
- if (PciRegisterData->AndValue != VALUE_NOCARE) {\r
- TempValue &= AndValue;\r
- }\r
- if (PciRegisterData->OrValue != VALUE_NOCARE) {\r
- TempValue |= OrValue;\r
- }\r
-\r
- switch (Width) {\r
- case EfiPciWidthUint8:\r
- *(UINT8 *)Buffer = (UINT8) TempValue;\r
- break;\r
-\r
- case EfiPciWidthUint16:\r
- *(UINT16 *)Buffer = (UINT16) TempValue;\r
- break;\r
- case EfiPciWidthUint32:\r
- *(UINT32 *)Buffer = TempValue;\r
- break;\r
-\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- Write PCI device configuration register by specified address.\r
-\r
- This function check the incompatiblilites on PCI device, and write date\r
- into register.\r
-\r
- @param PciRootBridgeIo PCI root bridge io instance.\r
- @param PciIo PCI IO protocol instance.\r
- @param PciDeviceInfo PCI device information.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval other Some error occurred when writing PCI device information\r
- or checking incompatibility.\r
-\r
-**/\r
-EFI_STATUS\r
-WriteConfigData (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 Width,\r
- IN UINT64 Offset,\r
- IN VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT64 AccessWidth;\r
- EFI_PCI_REGISTER_ACCESS_DATA *PciRegisterAccessData;\r
- UINT64 AccessAddress;\r
- UINTN Stride;\r
- UINT8 *Pointer;\r
- UINT64 Data;\r
- UINTN Shift;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
- ASSERT (Buffer != NULL);\r
-\r
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT) != 0) {\r
- //\r
- // Check access compatibility at first time\r
- //\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, Offset & 0xff, Width, &PciRegisterAccessData);\r
-\r
- if (Status == EFI_SUCCESS) {\r
- //\r
- // There exists incompatibility on this operation\r
- //\r
- AccessWidth = Width;\r
-\r
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {\r
- AccessWidth = PciRegisterAccessData->Width;\r
- }\r
-\r
- AccessAddress = Offset & ~((1 << AccessWidth) - 1);\r
-\r
- Stride = 0;\r
- Pointer = (UINT8 *) &Buffer;\r
- Data = * (UINT64 *) Buffer;\r
-\r
- while (TRUE) {\r
-\r
- if (AccessWidth > Width) {\r
- //\r
- // If actual access width is larger than orignal one, additional data need to be read back firstly\r
- //\r
- Status = ReadConfigData (PciRootBridgeIo, PciIo, PciDeviceInfo, AccessWidth, AccessAddress, &Data);\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- //\r
- // Check data read incompatibility\r
- //\r
- UpdateConfigData (PciDeviceInfo, PCI_REGISTER_READ, AccessWidth, AccessAddress & 0xff, &Data);\r
-\r
- Shift = (UINTN)(Offset - AccessAddress) * 8;\r
- switch (Width) {\r
- case EfiPciWidthUint8:\r
- Data = (* (UINT8 *) Buffer) << Shift | (Data & ~(0xff << Shift));\r
- break;\r
-\r
- case EfiPciWidthUint16:\r
- Data = (* (UINT16 *) Buffer) << Shift | (Data & ~(0xffff << Shift));\r
- break;\r
- }\r
-\r
- //\r
- // Check data write incompatibility\r
- //\r
- UpdateConfigData (PciDeviceInfo, PCI_REGISTER_WRITE, AccessWidth, MultU64x32 (AccessAddress, 0xff), &Data);\r
- }\r
-\r
- if (PciRootBridgeIo != NULL) {\r
- Status = PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) AccessWidth,\r
- AccessAddress,\r
- 1,\r
- &Data\r
- );\r
- } else {\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) AccessWidth,\r
- (UINT32) AccessAddress,\r
- 1,\r
- &Data\r
- );\r
- }\r
-\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- Data = RShiftU64 (Data, ((1 << AccessWidth) * 8));\r
-\r
- Stride = (UINTN)1 << AccessWidth;\r
- AccessAddress += Stride;\r
- if (AccessAddress >= (Offset + LShiftU64 (1ULL, (UINTN)Width))) {\r
- //\r
- // If all datas have been written, exit\r
- //\r
- break;\r
- }\r
-\r
- Pointer += Stride;\r
-\r
- if ((AccessAddress & 0xff) < PciRegisterAccessData->EndOffset) {\r
- //\r
- // If current offset doesn't reach the end\r
- //\r
- continue;\r
- }\r
-\r
- //\r
- // Continue checking access incompatibility\r
- //\r
- Status = PciRegisterAccessCheck (PciDeviceInfo, PCI_REGISTER_WRITE, AccessAddress & 0xff, AccessWidth, &PciRegisterAccessData);\r
- if (Status == EFI_SUCCESS) {\r
- if (PciRegisterAccessData->Width != VALUE_NOCARE) {\r
- AccessWidth = PciRegisterAccessData->Width;\r
- }\r
- }\r
- };\r
-\r
- return Status;\r
- }\r
-\r
- }\r
- //\r
- // AccessWidth incompatible check not supportted\r
- // or, there doesn't exist incompatibility on this operation\r
- //\r
- if (PciRootBridgeIo != NULL) {\r
- Status = PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
- Offset,\r
- 1,\r
- Buffer\r
- );\r
- } else {\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) Width,\r
- (UINT32) Offset,\r
- 1,\r
- Buffer\r
- );\r
- }\r
-\r
- return Status;\r
-}\r
-\r
-/**\r
- Abstract PCI device device information.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to EFI_PCI_PROTOCOL.\r
- @param Pci PCI device configuration space.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
-\r
- @retval EFI_SUCCESS Pci device device information has been abstracted.\r
- @retval EFI_NOT_FOUND Cannot found the specified PCI device.\r
- @retval other Some error occurred when reading PCI device information.\r
-\r
-**/\r
-EFI_STATUS\r
-GetPciDeviceDeviceInfo (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN UINT64 Offset, OPTIONAL\r
- OUT EFI_PCI_DEVICE_INFO *PciDeviceInfo\r
-)\r
-{\r
- EFI_STATUS Status;\r
- UINT64 PciAddress;\r
- UINT32 PciConfigData;\r
- PCI_IO_DEVICE *PciIoDevice;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
- ASSERT (PciDeviceInfo != NULL);\r
-\r
- if (PciIo != NULL) {\r
- PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
-\r
- //\r
- // Get pointer to PCI_TYPE00 from PciIoDevice\r
- //\r
- Pci = &PciIoDevice->Pci;\r
- }\r
-\r
- if (Pci == NULL) {\r
- //\r
- // While PCI_TYPE00 hasn't been gotten, read PCI device device information directly\r
- //\r
- PciAddress = Offset & 0xffffffffffffff00ULL;\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- PciAddress,\r
- 1,\r
- &PciConfigData\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- if ((PciConfigData & 0xffff) == 0xffff) {\r
- return EFI_NOT_FOUND;\r
- }\r
-\r
- PciDeviceInfo->VendorID = PciConfigData & 0xffff;\r
- PciDeviceInfo->DeviceID = PciConfigData >> 16;\r
-\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- PciAddress + 8,\r
- 1,\r
- &PciConfigData\r
- );\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- PciDeviceInfo->RevisionID = PciConfigData & 0xf;\r
-\r
- Status = PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- EfiPciWidthUint32,\r
- PciAddress + 0x2c,\r
- 1,\r
- &PciConfigData\r
- );\r
-\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- PciDeviceInfo->SubsystemVendorID = PciConfigData & 0xffff;\r
- PciDeviceInfo->SubsystemID = PciConfigData >> 16;\r
-\r
- } else {\r
- PciDeviceInfo->VendorID = Pci->Hdr.VendorId;\r
- PciDeviceInfo->DeviceID = Pci->Hdr.DeviceId;\r
- PciDeviceInfo->RevisionID = Pci->Hdr.RevisionID;\r
- PciDeviceInfo->SubsystemVendorID = Pci->Device.SubsystemVendorID;\r
- PciDeviceInfo->SubsystemID = Pci->Device.SubsystemID;\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Read PCI configuration space with incompatibility check.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_UNSUPPORTED Buffer is NULL.\r
- @retval other Some error occurred when reading PCI configuration space.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIncompatibilityCheckRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN UINTN Width,\r
- IN UINT64 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
- UINT32 Stride;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
- if (Buffer == NULL) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // get PCI device device information\r
- //\r
- Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- Stride = 1 << Width;\r
-\r
- for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *)Buffer + Stride) {\r
-\r
- //\r
- // read configuration register\r
- //\r
- Status = ReadConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, (UINT64) Width, Offset, Buffer);\r
-\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- //\r
- // update the data read from configuration register\r
- //\r
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
- UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_READ, Width, Offset & 0xff, Buffer);\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Write PCI configuration space with incompatibility check.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be write.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI configuration header of the PCI controller.\r
- Buffer is NULL.\r
- @retval other Some error occurred when writing PCI configuration space.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIncompatibilityCheckWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, OPTIONAL\r
- IN EFI_PCI_IO_PROTOCOL *PciIo, OPTIONAL\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN UINTN Width,\r
- IN UINT64 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_PCI_DEVICE_INFO PciDeviceInfo;\r
- UINT32 Stride;\r
- UINT64 Data;\r
-\r
- ASSERT ((PciRootBridgeIo == NULL) ^ (PciIo == NULL));\r
- if (Buffer == NULL) {\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // Get PCI device device information\r
- //\r
- Status = GetPciDeviceDeviceInfo (PciRootBridgeIo, PciIo, Pci, Offset, &PciDeviceInfo);\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
-\r
- Stride = 1 << Width;\r
-\r
- for (; Count > 0; Count--, Offset += Stride, Buffer = (UINT8 *) Buffer + Stride) {\r
-\r
- Data = 0;\r
-\r
- switch (Width) {\r
- case EfiPciWidthUint8:\r
- Data = * (UINT8 *) Buffer;\r
- break;\r
- case EfiPciWidthUint16:\r
- Data = * (UINT16 *) Buffer;\r
- break;\r
-\r
- case EfiPciWidthUint32:\r
- Data = * (UINT32 *) Buffer;\r
- break;\r
-\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
-\r
- //\r
- // Update the data writen into configuration register\r
- //\r
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT) != 0) {\r
- UpdateConfigData (&PciDeviceInfo, PCI_REGISTER_WRITE, Width, Offset & 0xff, &Data);\r
- }\r
-\r
- //\r
- // Write configuration register\r
- //\r
- Status = WriteConfigData (PciRootBridgeIo, PciIo, &PciDeviceInfo, Width, Offset, &Data);\r
-\r
- if (Status != EFI_SUCCESS) {\r
- return Status;\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
- Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciRootBridgeIoRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {\r
- //\r
- // If PCI incompatibility check enabled\r
- //\r
- Status = PciIncompatibilityCheckRead (\r
- PciRootBridgeIo,\r
- NULL,\r
- Pci,\r
- (UINTN) Width,\r
- Offset,\r
- Count,\r
- Buffer\r
- );\r
- if (Status == EFI_UNSUPPORTED) {\r
- return EFI_INVALID_PARAMETER;\r
- } else {\r
- return Status;\r
- }\r
- } else {\r
- return PciRootBridgeIo->Pci.Read (\r
- PciRootBridgeIo,\r
- Width,\r
- Offset,\r
- Count,\r
- Buffer\r
- );\r
- }\r
-}\r
-\r
-/**\r
- Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciRootBridgeIoWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {\r
- //\r
- // If PCI incompatibility check enabled\r
- //\r
- Status = PciIncompatibilityCheckWrite (\r
- PciRootBridgeIo,\r
- NULL,\r
- Pci,\r
- Width,\r
- Offset,\r
- Count,\r
- Buffer\r
- );\r
- if (Status == EFI_UNSUPPORTED) {\r
- return EFI_INVALID_PARAMETER;\r
- } else {\r
- return Status;\r
- }\r
-\r
- } else {\r
- return PciRootBridgeIo->Pci.Write (\r
- PciRootBridgeIo,\r
- Width,\r
- Offset,\r
- Count,\r
- Buffer\r
- );\r
- }\r
-}\r
-\r
-/**\r
- Read PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
-\r
- @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoRead (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_READ_SUPPORT) != 0) {\r
- //\r
- // If PCI incompatibility check enabled\r
- //\r
- return PciIncompatibilityCheckRead (\r
- NULL,\r
- PciIo,\r
- NULL,\r
- (UINTN) Width,\r
- Offset,\r
- Count,\r
- Buffer\r
- );\r
- } else {\r
- return PciIo->Pci.Read (\r
- PciIo,\r
- Width,\r
- Offset,\r
- Count,\r
- Buffer\r
- );\r
- }\r
-}\r
-\r
-/**\r
- Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
-\r
- If PCI incompatibility check is enabled, do incompatibility check.\r
-\r
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of PCI configuration operations to perform.\r
- @param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoWrite (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- if ((PcdGet8 (PcdPciIncompatibleDeviceSupportMask) & PCI_INCOMPATIBLE_WRITE_SUPPORT) != 0) {\r
- //\r
- // If PCI incompatibility check enabled\r
- //\r
- return PciIncompatibilityCheckWrite (\r
- NULL,\r
- PciIo,\r
- NULL,\r
- Width,\r
- Offset,\r
- Count,\r
- Buffer\r
- );\r
-\r
- } else {\r
- return PciIo->Pci.Write (\r
- PciIo,\r
- Width,\r
- Offset,\r
- Count,\r
- Buffer\r
- );\r
- }\r
-}\r
-\r
#ifndef _EFI_PCI_LIB_H_\r
#define _EFI_PCI_LIB_H_\r
\r
-//\r
-// Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask\r
-//\r
-#define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01\r
-#define PCI_INCOMPATIBLE_READ_SUPPORT 0x02\r
-#define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04\r
-#define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08\r
-#define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x10\r
\r
typedef struct {\r
EFI_HANDLE Handle;\r
**/\r
EFI_STATUS\r
PciHostBridgeEnumerator (\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
- );\r
-\r
-/**\r
- Read PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
-\r
- @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoRead (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r
-\r
- If PCI incompatibility check is enabled, do incompatibility check.\r
-\r
- @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of PCI configuration operations to perform.\r
- @param Buffer For read operations, the destination buffer to store the results. For write\r
- operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
- @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
- valid for the PCI configuration header of the PCI controller.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoWrite (\r
- IN EFI_PCI_IO_PROTOCOL *PciIo,\r
- IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
- IN UINT32 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciRootBridgeIoWrite (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci,\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
- );\r
-\r
-/**\r
- Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-\r
- @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
- @param Pci A pointer to PCI_TYPE00.\r
- @param Width Signifies the width of the memory operations.\r
- @param Offset The offset within the PCI configuration space for the PCI controller.\r
- @param Count The number of unit to be read.\r
- @param Buffer For read operations, the destination buffer to store the results. For\r
- write operations, the source buffer to write data from.\r
-\r
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
- @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-PciRootBridgeIoRead (\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
- IN PCI_TYPE00 *Pci, OPTIONAL\r
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Offset,\r
- IN UINTN Count,\r
- IN OUT VOID *Buffer\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r
);\r
\r
#endif\r
}\r
\r
/**\r
- Get Pci device's oprom infor bits.\r
+ Get Pci device's oprom information.\r
\r
- @param PciIoDevice Pci device instance.\r
+ @param PciIoDevice Input Pci device instance.\r
+ Output Pci device instance with updated OptionRom size.\r
\r
@retval EFI_NOT_FOUND Pci device has not Option Rom.\r
@retval EFI_SUCCESS Pci device has Option Rom.\r
**/\r
EFI_STATUS\r
GetOpRomInfo (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN OUT PCI_IO_DEVICE *PciIoDevice\r
)\r
{\r
UINT8 RomBarIndex;\r
\r
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {\r
//\r
- // If is ppb\r
- //\r
-\r
- //\r
- // 0x38\r
+ // If is ppb, 0x38\r
//\r
RomBarIndex = PCI_BRIDGE_ROMBAR;\r
}\r
AllOnes = 0xfffffffe;\r
Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);\r
\r
- Status = PciRootBridgeIoWrite (\r
+ Status = PciRootBridgeIo->Pci.Write (\r
PciRootBridgeIo,\r
- &PciIoDevice->Pci,\r
EfiPciWidthUint32,\r
Address,\r
1,\r
//\r
// Read back\r
//\r
- Status = PciRootBridgeIoRead (\r
+ Status = PciRootBridgeIo->Pci.Read(\r
PciRootBridgeIo,\r
- &PciIoDevice->Pci,\r
EfiPciWidthUint32,\r
Address,\r
1,\r
if (EFI_ERROR (Status)) {\r
return EFI_NOT_FOUND;\r
}\r
+\r
//\r
// Bits [1, 10] are reserved\r
//\r
// Clear all bars\r
//\r
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {\r
- PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);\r
+ PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);\r
}\r
\r
//\r
// enable its decoder\r
//\r
Value32 = RomBar | 0x1;\r
- PciIoWrite (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,\r
- RomBarIndex,\r
- 1,\r
- &Value32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,\r
+ RomBarIndex,\r
+ 1,\r
+ &Value32\r
+ );\r
\r
//\r
// Programe all upstream bridge\r
// disable rom decode\r
//\r
Value32 = 0xFFFFFFFE;\r
- PciIoWrite (\r
- PciIo,\r
- (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,\r
- RomBarIndex,\r
- 1,\r
- &Value32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,\r
+ RomBarIndex,\r
+ 1,\r
+ &Value32\r
+ );\r
\r
}\r
}\r
\r
\r
/**\r
- Get Pci device's oprom infor bits.\r
+ Get Pci device's oprom information.\r
\r
- @param PciIoDevice Pci device instance.\r
+ @param PciIoDevice Input Pci device instance.\r
+ Output Pci device instance with updated OptionRom size.\r
\r
@retval EFI_NOT_FOUND Pci device has not Option Rom.\r
@retval EFI_SUCCESS Pci device has Option Rom.\r
**/\r
EFI_STATUS\r
GetOpRomInfo (\r
- IN PCI_IO_DEVICE *PciIoDevice\r
+ IN OUT PCI_IO_DEVICE *PciIoDevice\r
);\r
\r
/**\r
//\r
// Write PMCSR\r
//\r
- PciIoWrite (\r
- &PciIoDevice->PciIo,\r
- EfiPciIoWidthUint16,\r
- PowerManagementRegBlock + 4,\r
- 1,\r
- &PowerManagementCSR\r
- );\r
+ PciIoDevice->PciIo.Pci.Write (\r
+ &PciIoDevice->PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PowerManagementRegBlock + 4,\r
+ 1,\r
+ &PowerManagementCSR\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
VOID\r
InsertResourceNode (\r
- IN PCI_RESOURCE_NODE *Bridge,\r
- IN PCI_RESOURCE_NODE *ResNode\r
+ IN OUT PCI_RESOURCE_NODE *Bridge,\r
+ IN PCI_RESOURCE_NODE *ResNode\r
)\r
{\r
LIST_ENTRY *CurrentLink;\r
//\r
// Apply padding resource if available\r
//\r
-\r
Offset = Aperture & (Node->Alignment);\r
\r
if (Offset != 0) {\r
//\r
// Consider the aperture alignment\r
//\r
-\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
\r
**/\r
VOID\r
GetResourceFromDevice (\r
- IN PCI_IO_DEVICE *PciDev,\r
- IN PCI_RESOURCE_NODE *IoNode,\r
- IN PCI_RESOURCE_NODE *Mem32Node,\r
- IN PCI_RESOURCE_NODE *PMem32Node,\r
- IN PCI_RESOURCE_NODE *Mem64Node,\r
- IN PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN OUT PCI_RESOURCE_NODE *IoNode,\r
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
\r
\r
Node = NULL;\r
\r
- Node = AllocatePool (sizeof (PCI_RESOURCE_NODE));\r
+ Node = AllocateZeroPool (sizeof (PCI_RESOURCE_NODE));\r
ASSERT (Node != NULL);\r
if (Node == NULL) {\r
return NULL;\r
}\r
\r
- ZeroMem (Node, sizeof (PCI_RESOURCE_NODE));\r
-\r
Node->Signature = PCI_RESOURCE_SIGNATURE;\r
Node->PciDev = PciDev;\r
Node->Length = Length;\r
**/\r
VOID\r
CreateResourceMap (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN PCI_RESOURCE_NODE *IoNode,\r
- IN PCI_RESOURCE_NODE *Mem32Node,\r
- IN PCI_RESOURCE_NODE *PMem32Node,\r
- IN PCI_RESOURCE_NODE *Mem64Node,\r
- IN PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *Bridge,\r
+ IN OUT PCI_RESOURCE_NODE *IoNode,\r
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem64Node\r
)\r
{\r
PCI_IO_DEVICE *Temp;\r
IoBridge\r
);\r
} else {\r
- gBS->FreePool (IoBridge);\r
+ FreePool (IoBridge);\r
IoBridge = NULL;\r
}\r
\r
Mem32Bridge\r
);\r
} else {\r
- gBS->FreePool (Mem32Bridge);\r
+ FreePool (Mem32Bridge);\r
Mem32Bridge = NULL;\r
}\r
\r
PMem32Bridge\r
);\r
} else {\r
- gBS->FreePool (PMem32Bridge);\r
+ FreePool (PMem32Bridge);\r
PMem32Bridge = NULL;\r
}\r
\r
Mem64Bridge\r
);\r
} else {\r
- gBS->FreePool (Mem64Bridge);\r
+ FreePool (Mem64Bridge);\r
Mem64Bridge = NULL;\r
}\r
\r
PMem64Bridge\r
);\r
} else {\r
- gBS->FreePool (PMem64Bridge);\r
+ FreePool (PMem64Bridge);\r
PMem64Bridge = NULL;\r
}\r
\r
//\r
// If it is P2C, apply hard coded resource padding\r
//\r
- //\r
if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {\r
ResourcePaddingForCardBusBridge (\r
Temp,\r
\r
CurrentLink = CurrentLink->ForwardLink;\r
}\r
- //\r
+\r
//\r
// To do some platform specific resource padding ...\r
//\r
case PciBarTypeMem32:\r
case PciBarTypePMem32:\r
\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
\r
\r
Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);\r
\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) RShiftU64 (Address, 32);\r
\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
\r
\r
case PPB_BAR_0:\r
case PPB_BAR_1:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
case PPB_IO_RANGE:\r
\r
Address32 = ((UINT32) (Address)) >> 8;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- 0x1C,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ 0x1C,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 >>= 8;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x30,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x30,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) (Address + Node->Length - 1);\r
Address32 = ((UINT32) (Address32)) >> 8;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- 0x1D,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ 0x1D,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 >>= 8;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x32,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x32,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
case PPB_MEM32_RANGE:\r
\r
Address32 = ((UINT32) (Address)) >> 16;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x20,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x20,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) (Address + Node->Length - 1);\r
Address32 = ((UINT32) (Address32)) >> 16;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x22,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x22,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
case PPB_PMEM64_RANGE:\r
\r
Address32 = ((UINT32) (Address)) >> 16;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x24,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x24,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) (Address + Node->Length - 1);\r
Address32 = ((UINT32) (Address32)) >> 16;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- 0x26,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ 0x26,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) RShiftU64 (Address, 32);\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x28,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ 0x28,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Address32 = (UINT32) RShiftU64 ((Address + Node->Length - 1), 32);\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x2C,\r
- 1,\r
- &Address32\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ 0x2C,\r
+ 1,\r
+ &Address32\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
switch (Node->Bar) {\r
\r
case P2C_BAR_0:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- (Node->PciDev->PciBar[Node->Bar]).Offset,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+ 1,\r
+ &Address\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
break;\r
\r
case P2C_MEM_1:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_MEMORY_BASE_0,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_0,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_MEMORY_LIMIT_0,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_LIMIT_0,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
if (Node->ResType == PciBarTypeMem32) {\r
//\r
// Set non-prefetchable bit\r
//\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- PCI_CARD_BRIDGE_CONTROL,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
\r
BridgeControl &= (UINT16) ~PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- PCI_CARD_BRIDGE_CONTROL,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
\r
} else {\r
//\r
// Set pre-fetchable bit\r
//\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- PCI_CARD_BRIDGE_CONTROL,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
\r
BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- PCI_CARD_BRIDGE_CONTROL,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
}\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
break;\r
\r
case P2C_MEM_2:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_MEMORY_BASE_1,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_BASE_1,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_MEMORY_LIMIT_1,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_MEMORY_LIMIT_1,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
if (Node->ResType == PciBarTypeMem32) {\r
\r
//\r
// Set non-prefetchable bit\r
//\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- PCI_CARD_BRIDGE_CONTROL,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
\r
BridgeControl &= (UINT16) ~(PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE);\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- PCI_CARD_BRIDGE_CONTROL,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
\r
} else {\r
\r
//\r
// Set pre-fetchable bit\r
//\r
- PciIoRead (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- PCI_CARD_BRIDGE_CONTROL,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
\r
BridgeControl |= PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint16,\r
- PCI_CARD_BRIDGE_CONTROL,\r
- 1,\r
- &BridgeControl\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint16,\r
+ PCI_CARD_BRIDGE_CONTROL,\r
+ 1,\r
+ &BridgeControl\r
+ );\r
}\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
break;\r
\r
case P2C_IO_1:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_IO_BASE_0_LOWER,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_0_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_IO_LIMIT_0_LOWER,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_LIMIT_0_LOWER,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
break;\r
\r
case P2C_IO_2:\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_IO_BASE_1_LOWER,\r
- 1,\r
- &Address\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_BASE_1_LOWER,\r
+ 1,\r
+ &Address\r
+ );\r
\r
TempAddress = Address + Node->Length - 1;\r
- PciIoWrite (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- PCI_CARD_IO_LIMIT_1_LOWER,\r
- 1,\r
- &TempAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ PCI_CARD_IO_LIMIT_1_LOWER,\r
+ 1,\r
+ &TempAddress\r
+ );\r
\r
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
Node->PciDev->PciBar[Node->Bar].Length = Node->Length;\r
**/\r
VOID\r
InsertResourceNode (\r
- IN PCI_RESOURCE_NODE *Bridge,\r
- IN PCI_RESOURCE_NODE *ResNode\r
+ IN OUT PCI_RESOURCE_NODE *Bridge,\r
+ IN PCI_RESOURCE_NODE *ResNode\r
);\r
\r
/**\r
**/\r
VOID\r
GetResourceFromDevice (\r
- IN PCI_IO_DEVICE *PciDev,\r
- IN PCI_RESOURCE_NODE *IoNode,\r
- IN PCI_RESOURCE_NODE *Mem32Node,\r
- IN PCI_RESOURCE_NODE *PMem32Node,\r
- IN PCI_RESOURCE_NODE *Mem64Node,\r
- IN PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *PciDev,\r
+ IN OUT PCI_RESOURCE_NODE *IoNode,\r
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem64Node\r
);\r
\r
/**\r
**/\r
VOID\r
CreateResourceMap (\r
- IN PCI_IO_DEVICE *Bridge,\r
- IN PCI_RESOURCE_NODE *IoNode,\r
- IN PCI_RESOURCE_NODE *Mem32Node,\r
- IN PCI_RESOURCE_NODE *PMem32Node,\r
- IN PCI_RESOURCE_NODE *Mem64Node,\r
- IN PCI_RESOURCE_NODE *PMem64Node\r
+ IN PCI_IO_DEVICE *Bridge,\r
+ IN OUT PCI_RESOURCE_NODE *IoNode,\r
+ IN OUT PCI_RESOURCE_NODE *Mem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem32Node,\r
+ IN OUT PCI_RESOURCE_NODE *Mem64Node,\r
+ IN OUT PCI_RESOURCE_NODE *PMem64Node\r
);\r
\r
/**\r
+++ /dev/null
-/** @file\r
- PCI Incompatible device support Libary. Platform can implement an\r
- instance to support the incompatible PCI devices.\r
-\r
-Copyright (c) 2006 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __PCI_INCOMPATIBLE_DEVICE_SUPPORT_LIB_H__\r
-#define __PCI_INCOMPATIBLE_DEVICE_SUPPORT_LIB_H__\r
-\r
-#define PCI_REGISTER_READ 0xfffffffffffffff1ULL\r
-#define PCI_REGISTER_WRITE 0xfffffffffffffff2ULL\r
-#define VALUE_NOCARE 0xffffffffffffffffULL\r
-\r
-//\r
-// PCI device device information\r
-//\r
-typedef struct {\r
- UINT64 VendorID;\r
- UINT64 DeviceID;\r
- UINT64 RevisionID;\r
- UINT64 SubsystemVendorID;\r
- UINT64 SubsystemID;\r
-} EFI_PCI_DEVICE_INFO;\r
-\r
-\r
-//\r
-// store hardcode value of resgister\r
-//\r
-typedef struct {\r
- UINT64 AndValue;\r
- UINT64 OrValue;\r
-} EFI_PCI_REGISTER_VALUE_DATA;\r
-\r
-//\r
-// store access width information\r
-//\r
-typedef struct {\r
- UINT64 StartOffset;\r
- UINT64 EndOffset;\r
- UINT64 Width;\r
-} EFI_PCI_REGISTER_ACCESS_DATA;\r
-\r
-\r
-//\r
-// ACPI resource descriptor\r
-//\r
-typedef struct {\r
- UINT64 ResType;\r
- UINT64 GenFlag;\r
- UINT64 SpecificFlag;\r
- UINT64 AddrSpaceGranularity;\r
- UINT64 AddrRangeMin;\r
- UINT64 AddrRangeMax;\r
- UINT64 AddrTranslationOffset;\r
- UINT64 AddrLen;\r
-} EFI_PCI_RESOUCE_DESCRIPTOR;\r
-\r
-/**\r
- Check the incompatible device list for ACPI resource update and return\r
- the configuration.\r
-\r
- This function searches the incompatible device list according to request\r
- information. If the PCI device belongs to the devices list, corresponding\r
- configuration informtion will be returned, in the meantime return EFI_SUCCESS.\r
-\r
- @param PciDeviceInfo A pointer to PCI device information.\r
- @param Configuration Returned information.\r
-\r
- @retval EFI_SUCCESS If check incompatible device successfully.\r
- @retval EFI_ABORTED No any resource type.\r
- @retval EFI_OUT_OF_RESOURCES No memory available.\r
- @retval EFI_UNSUPPORTED Invalid Tag encounted.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciResourceUpdateCheck (\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- OUT VOID *Configuration\r
- );\r
-\r
-/**\r
- Check the incompatible device list and return configuraton register mask values.\r
-\r
- This function searches the incompatible device list according to request\r
- information. If the PCI device belongs to the devices list, corresponding\r
- configuration informtion will be returned, in the meantime return EFI_SUCCESS.\r
-\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
- @param AccessType Access Type, READ or WRITE.\r
- @param Offset The address within the PCI configuration space.\r
- @param Configuration Returned information.\r
-\r
- @retval EFI_SUCCESS If check incompatible device successfully.\r
- @retval EFI_UNSUPPORTED Failed to check incompatibility device.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciRegisterUpdateCheck (\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 AccessType,\r
- IN UINT64 Offset,\r
- OUT VOID *Configuration\r
- );\r
-\r
-/**\r
- Check the incompatible device list for access width incompatibility and\r
- return the configuration.\r
-\r
- This function searches the incompatible device list for access width\r
- incompatibility according to request information. If the PCI device\r
- belongs to the devices list, corresponding configuration informtion\r
- will be returned, in the meantime return EFI_SUCCESS.\r
-\r
- @param PciDeviceInfo A pointer to PCI device information.\r
- @param AccessType Access type, READ or WRITE.\r
- @param Offset The address within the PCI configuration space.\r
- @param AccessWidth Access width needs to check incompatibility.\r
- @param Configuration Returned information.\r
-\r
- @retval EFI_SUCCESS If check incompatible device successfully.\r
- @retval EFI_UNSUPPORTED Failed to check incompatibility device.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciRegisterAccessCheck (\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 AccessType,\r
- IN UINT64 Offset,\r
- IN UINT64 AccessWidth,\r
- OUT VOID *Configuration\r
- );\r
-\r
-#endif\r
-\r
Include # Root include for the package\r
\r
[LibraryClasses.common]\r
- ## @libraryclass This libary is used to support the incompatible PCI devices.\r
- PciIncompatibleDeviceSupportLib|Include/Library/PciIncompatibleDeviceSupportLib.h\r
-\r
## @libraryclass OEM status code libary is used to report status code to OEM device.\r
OemHookStatusCodeLib|Include/Library/OemHookStatusCodeLib.h\r
\r
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdIsaBusOnlySupportSlaveDma|FALSE|BOOLEAN|0x00010041\r
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdIsaBusSupportIsaMemory|TRUE|BOOLEAN|0x00010042\r
\r
-[PcdsFixedAtBuild]\r
- ## PCD marks PCI support incompatible operations: AcpiResource, Read, Write, RegisterUpdate, AccessWidth.\r
- # BIT0:AcpiResource, BIT1:Read, BIT2:Write, BIT3:RegisterUpdate, BIT4:AccessWidth\r
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask|0|UINT8|0x0001003f\r
-\r
[PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic]\r
## PcdStatusCodeMemorySize is used when PcdStatusCodeUseMemory is set to true\r
# (PcdStatusCodeMemorySize * KBytes) is the total taken memory size.\r
#\r
# This file is used to build all modules in IntelFrameworkModulePkg.\r
#\r
-# Copyright (c) 2007, Intel Corporation\r
+# Copyright (c) 2007 - 2009, Intel Corporation\r
#\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
- PciIncompatibleDeviceSupportLib|IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf\r
IoLib|IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.inf\r
\r
[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
- PciIncompatibleDeviceSupportLib|IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf\r
IoLib|IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeIoLibCpuIo.inf\r
\r
################################################################################\r
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0\r
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320\r
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPciIncompatibleDeviceSupportMask|0\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0xFFFB0000\r
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200\r
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8\r
IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
- IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf\r
IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf\r
IntelFrameworkModulePkg/Library/PeiRecoveryLib/PeiRecoveryLib.inf\r
IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+++ /dev/null
-/** @file\r
- The incompatible PCI device list template.\r
-\r
-Copyright (c) 2006 - 2009, Intel Corporation \r
-All rights reserved. This program and the accompanying materials \r
-are licensed and made available under the terms and conditions of the BSD License \r
-which accompanies this distribution. The full text of the license may be found at \r
-http://opensource.org/licenses/bsd-license.php \r
- \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-\r
-**/\r
-\r
-#ifndef _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_\r
-#define _EFI_INCOMPATIBLE_PCI_DEVICE_LIST_H_\r
-\r
-#include <Library/PciIncompatibleDeviceSupportLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-#include <IndustryStandard/Pci.h>\r
-#include <IndustryStandard/Acpi.h>\r
-\r
-\r
-#define PCI_DEVICE_ID(VendorId, DeviceId, Revision, SubVendorId, SubDeviceId) \\r
- VendorId, DeviceId, Revision, SubVendorId, SubDeviceId\r
-\r
-#define PCI_BAR_TYPE_IO ACPI_ADDRESS_SPACE_TYPE_IO\r
-#define PCI_BAR_TYPE_MEM ACPI_ADDRESS_SPACE_TYPE_MEM\r
-\r
-#define DEVICE_INF_TAG 0xFFF2\r
-#define DEVICE_RES_TAG 0xFFF1\r
-#define LIST_END_TAG 0x0000\r
-\r
-//\r
-// descriptor for access width of incompatible PCI device\r
-//\r
-typedef struct {\r
- UINT64 AccessType;\r
- UINT64 AccessWidth;\r
- EFI_PCI_REGISTER_ACCESS_DATA PciRegisterAccessData;\r
-} EFI_PCI_REGISTER_ACCESS_DESCRIPTOR;\r
-\r
-//\r
-// descriptor for register value of incompatible PCI device\r
-//\r
-typedef struct {\r
- UINT64 AccessType;\r
- UINT64 Offset;\r
- EFI_PCI_REGISTER_VALUE_DATA PciRegisterValueData;\r
-} EFI_PCI_REGISTER_VALUE_DESCRIPTOR;\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- The template of PCI incompatible device support libary.\r
-\r
-Copyright (c) 2006 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "IncompatiblePciDeviceList.h"\r
-\r
-//\r
-// the incompatible PCI devices list template for ACPI resource\r
-//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForResource[] = {\r
- //\r
- // DEVICE_INF_TAG,\r
- // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
- // DEVICE_RES_TAG,\r
- // ResType, GFlag , SFlag, Granularity, RangeMin,\r
- // RangeMax, Offset, AddrLen\r
- //\r
-\r
- //\r
- // Sample Device 1\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_BAR_TYPE_IO,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_BAR_EVEN_ALIGN,\r
- //PCI_BAR_ALL,\r
- //PCI_BAR_NOCHANGE,\r
-\r
- //\r
- // Sample Device 2\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_BAR_TYPE_IO,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_ACPI_UNUSED,\r
- //PCI_BAR_EVEN_ALIGN,\r
- //PCI_BAR_ALL,\r
- //PCI_BAR_NOCHANGE,\r
-\r
- //\r
- // The end of the list\r
- //\r
- LIST_END_TAG\r
-};\r
-\r
-//\r
-// the incompatible PCI devices list template for the values of configuration registers\r
-//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gIncompatiblePciDeviceListForRegister[] = {\r
- //\r
- // DEVICE_INF_TAG,\r
- // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
- // PCI_RES_TAG,\r
- // PCI_ACCESS_TYPE, PCI_CONFIG_ADDRESS,\r
- // AND_VALUE, OR_VALUE\r
-\r
- //\r
- // Sample Device 1\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_REGISTER_READ,\r
- //PCI_CAPBILITY_POINTER_OFFSET,\r
- //0xffffff00,\r
- //VALUE_NOCARE,\r
-\r
- //\r
- // Sample Device 2\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, 0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_REGISTER_READ,\r
- //PCI_CAPBILITY_POINTER_OFFSET,\r
- //0xffffff00,\r
- //VALUE_NOCARE,\r
-\r
- //\r
- // The end of the list\r
- //\r
- LIST_END_TAG\r
-};\r
-\r
-//\r
-// the incompatible PCI devices list template for the access width of configuration registers\r
-//\r
-GLOBAL_REMOVE_IF_UNREFERENCED UINT64 gDeviceListForAccessWidth[] = {\r
- //\r
- // DEVICE_INF_TAG,\r
- // PCI_DEVICE_ID (VendorID, DeviceID, Revision, SubVendorId, SubDeviceId),\r
- // DEVICE_RES_TAG,\r
- // PCI_ACCESS_TYPE, PCI_ACCESS_WIDTH,\r
- // START_ADDRESS, END_ADDRESS,\r
- // ACTUAL_PCI_ACCESS_WIDTH,\r
- //\r
-\r
- //\r
- // Sample Device\r
- //\r
- //DEVICE_INF_TAG,\r
- //PCI_DEVICE_ID(0xXXXX, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE, DEVICE_ID_NOCARE),\r
- //DEVICE_RES_TAG,\r
- //PCI_REGISTER_READ,\r
- //EfiPciWidthUint8,\r
- //0,\r
- //0xFF,\r
- //EfiPciWidthUint32,\r
- //\r
-\r
- //\r
- // The end of the list\r
- //\r
- LIST_END_TAG\r
-};\r
-\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_ACCESS_DATA mPciRegisterAccessData = {0, 0, 0}; \r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_REGISTER_VALUE_DATA mPciRegisterValueData = {0, 0};\r
- \r
-\r
-/**\r
- Check whether two PCI devices matched.\r
-\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
- @param Header A pointer to EFI_PCI_DEVICE_INFO.\r
-\r
- @retval EFI_SUCCESS Two PCI devices matched.\r
- @retval EFI_UNSUPPORTED Two PCI devices don't match.\r
-\r
-**/\r
-EFI_STATUS\r
-DeviceCheck (\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN EFI_PCI_DEVICE_INFO *Header\r
- )\r
-{\r
- //\r
- // See if the Header matches the parameters passed in\r
- //\r
- if (Header->VendorID != DEVICE_ID_NOCARE) {\r
- if (PciDeviceInfo->VendorID != Header->VendorID) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- if (Header->DeviceID != DEVICE_ID_NOCARE) {\r
- if (PciDeviceInfo->DeviceID != Header->DeviceID) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- if (Header->RevisionID != DEVICE_ID_NOCARE) {\r
- if (PciDeviceInfo->RevisionID != Header->RevisionID) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- if (Header->SubsystemVendorID != DEVICE_ID_NOCARE) {\r
- if (PciDeviceInfo->SubsystemVendorID != Header->SubsystemVendorID) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- if (Header->SubsystemID != DEVICE_ID_NOCARE) {\r
- if (PciDeviceInfo->SubsystemID != Header->SubsystemID) {\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-\r
-/**\r
- Check the incompatible device list for ACPI resource update and return\r
- the configuration.\r
-\r
- This function searches the incompatible device list according to request\r
- information. If the PCI device belongs to the devices list, corresponding\r
- configuration informtion will be returned, in the meantime return EFI_SUCCESS.\r
-\r
- @param PciDeviceInfo A pointer to PCI device information.\r
- @param Configuration Returned information.\r
-\r
- @retval EFI_SUCCESS If check incompatible device successfully.\r
- @retval EFI_ABORTED No any resource type.\r
- @retval EFI_OUT_OF_RESOURCES No memory available.\r
- @retval EFI_UNSUPPORTED Invalid Tag encounted.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciResourceUpdateCheck (\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- OUT VOID *Configuration\r
- )\r
-{\r
- UINT64 Tag;\r
- UINT64 *ListPtr;\r
- UINT64 *TempListPtr;\r
- EFI_PCI_DEVICE_INFO *Header;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AcpiPtr;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *OldAcpiPtr;\r
- EFI_PCI_RESOUCE_DESCRIPTOR *Dsc;\r
- EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;\r
- UINTN Index;\r
-\r
- ASSERT (PciDeviceInfo != NULL);\r
-\r
- //\r
- // Initialize the return value to NULL\r
- //\r
- * (VOID **) Configuration = NULL;\r
-\r
- ListPtr = gIncompatiblePciDeviceListForResource;\r
- while (*ListPtr != LIST_END_TAG) {\r
-\r
- Tag = *ListPtr;\r
-\r
- switch (Tag) {\r
- case DEVICE_INF_TAG:\r
- Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);\r
- ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);\r
-\r
- if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {\r
- continue;\r
- }\r
-\r
- //\r
- // Matched an item, so construct the ACPI descriptor for the resource.\r
- //\r
- //\r
- // Count the resource items so that to allocate space\r
- //\r
- for (Index = 0, TempListPtr = ListPtr; *TempListPtr == DEVICE_RES_TAG; Index++) {\r
- TempListPtr = TempListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));\r
- }\r
- //\r
- // If there is at least one type of resource request,\r
- // allocate a acpi resource node\r
- //\r
- if (Index == 0) {\r
- return EFI_ABORTED;\r
- }\r
-\r
- AcpiPtr = AllocateZeroPool (\r
- sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Index + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)\r
- );\r
- if (AcpiPtr == NULL) {\r
- return EFI_OUT_OF_RESOURCES;\r
- }\r
-\r
- OldAcpiPtr = AcpiPtr;\r
-\r
- //\r
- // Fill the EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR structure\r
- // according to the EFI_PCI_RESOUCE_DESCRIPTOR structure\r
- //\r
- for (; *ListPtr == DEVICE_RES_TAG;) {\r
-\r
- Dsc = (EFI_PCI_RESOUCE_DESCRIPTOR *) (ListPtr + 1);\r
-\r
- AcpiPtr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
- AcpiPtr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
- AcpiPtr->ResType = (UINT8) Dsc->ResType;\r
- AcpiPtr->GenFlag = (UINT8) Dsc->GenFlag;\r
- AcpiPtr->SpecificFlag = (UINT8) Dsc->SpecificFlag;\r
- AcpiPtr->AddrSpaceGranularity = Dsc->AddrSpaceGranularity;;\r
- AcpiPtr->AddrRangeMin = Dsc->AddrRangeMin;\r
- AcpiPtr->AddrRangeMax = Dsc->AddrRangeMax;\r
- AcpiPtr->AddrTranslationOffset = Dsc->AddrTranslationOffset;\r
- AcpiPtr->AddrLen = Dsc->AddrLen;\r
-\r
- ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));\r
- AcpiPtr++;\r
- }\r
- //\r
- // put the checksum\r
- //\r
- PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (AcpiPtr);\r
- PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;\r
- PtrEnd->Checksum = 0;\r
-\r
- *(VOID **) Configuration = OldAcpiPtr;\r
-\r
- return EFI_SUCCESS;\r
-\r
- case DEVICE_RES_TAG:\r
- //\r
- // Adjust the pointer to the next PCI resource descriptor item\r
- //\r
- ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_RESOUCE_DESCRIPTOR)) / sizeof (UINT64));\r
- break;\r
-\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- return EFI_UNSUPPORTED;\r
-\r
-}\r
-\r
-/**\r
- Check the incompatible device list and return configuraton register mask values.\r
-\r
- This function searches the incompatible device list according to request\r
- information. If the PCI device belongs to the devices list, corresponding\r
- configuration informtion will be returned, in the meantime return EFI_SUCCESS.\r
-\r
- @param PciDeviceInfo A pointer to EFI_PCI_DEVICE_INFO.\r
- @param AccessType Access Type, READ or WRITE.\r
- @param Offset The address within the PCI configuration space.\r
- @param Configuration Returned information.\r
-\r
- @retval EFI_SUCCESS If check incompatible device successfully.\r
- @retval EFI_UNSUPPORTED Failed to check incompatibility device.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciRegisterUpdateCheck (\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 AccessType,\r
- IN UINT64 Offset,\r
- OUT VOID *Configuration\r
- )\r
-{\r
- EFI_PCI_DEVICE_INFO *Header;\r
- UINT64 Tag;\r
- UINT64 *ListPtr;\r
- EFI_PCI_REGISTER_VALUE_DATA *RegisterPtr;\r
- EFI_PCI_REGISTER_VALUE_DATA *Dsc;\r
-\r
- ASSERT (PciDeviceInfo != NULL);\r
-\r
- ListPtr = gIncompatiblePciDeviceListForRegister;\r
-\r
- //\r
- // Initialize the return value to NULL\r
- //\r
- * (VOID **) Configuration = NULL;\r
-\r
- while (*ListPtr != LIST_END_TAG) {\r
-\r
- Tag = *ListPtr;\r
-\r
- switch (Tag) {\r
- case DEVICE_INF_TAG:\r
- Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);\r
- ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);\r
-\r
- //\r
- // Check whether the PCI device matches the device in the incompatible devices list?\r
- // If not, ship next\r
- //\r
- if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {\r
- continue;\r
- }\r
-\r
- //\r
- // Matched an item, check whether access matches?\r
- //\r
- for (; *ListPtr == DEVICE_RES_TAG;) {\r
- ListPtr ++;\r
- if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->Offset == (Offset & 0xfc)) {\r
- if (((EFI_PCI_REGISTER_VALUE_DESCRIPTOR *)ListPtr)->AccessType == AccessType) {\r
-\r
- Dsc = (EFI_PCI_REGISTER_VALUE_DATA *) (ListPtr + 2);\r
- \r
- RegisterPtr = &mPciRegisterValueData;\r
-\r
- RegisterPtr->AndValue = Dsc->AndValue;\r
- RegisterPtr->OrValue = Dsc->OrValue;\r
-\r
- *(VOID **) Configuration = RegisterPtr;\r
-\r
- return EFI_SUCCESS;\r
- }\r
- }\r
- ListPtr += sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR) / (sizeof (UINT64));\r
- }\r
- return EFI_UNSUPPORTED;\r
-\r
- case DEVICE_RES_TAG:\r
- //\r
- // Adjust the pointer to the next item\r
- //\r
- ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_VALUE_DESCRIPTOR)) / sizeof (UINT64));\r
- break;\r
-\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- return EFI_UNSUPPORTED;\r
-}\r
-\r
-/**\r
- Check the incompatible device list for access width incompatibility and\r
- return the configuration.\r
-\r
- This function searches the incompatible device list for access width\r
- incompatibility according to request information. If the PCI device\r
- belongs to the devices list, corresponding configuration informtion\r
- will be returned, in the meantime return EFI_SUCCESS.\r
-\r
- @param PciDeviceInfo A pointer to PCI device information.\r
- @param AccessType Access type, READ or WRITE.\r
- @param Offset The address within the PCI configuration space.\r
- @param AccessWidth Access width needs to check incompatibility.\r
- @param Configuration Returned information.\r
-\r
- @retval EFI_SUCCESS If check incompatible device successfully.\r
- @retval EFI_UNSUPPORTED Failed to check incompatibility device.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciRegisterAccessCheck (\r
- IN EFI_PCI_DEVICE_INFO *PciDeviceInfo,\r
- IN UINT64 AccessType,\r
- IN UINT64 Offset,\r
- IN UINT64 AccessWidth,\r
- OUT VOID *Configuration\r
- )\r
-{\r
- EFI_PCI_DEVICE_INFO *Header;\r
- UINT64 Tag;\r
- UINT64 *ListPtr;\r
- EFI_PCI_REGISTER_ACCESS_DATA *RegisterPtr;\r
- EFI_PCI_REGISTER_ACCESS_DATA *Dsc;\r
-\r
- ASSERT (PciDeviceInfo != NULL);\r
-\r
- ListPtr = gDeviceListForAccessWidth;\r
-\r
- //\r
- // Initialize the return value to NULL\r
- //\r
- * (VOID **) Configuration = NULL;\r
-\r
- while (*ListPtr != LIST_END_TAG) {\r
-\r
- Tag = *ListPtr;\r
-\r
- switch (Tag) {\r
- case DEVICE_INF_TAG:\r
- Header = (EFI_PCI_DEVICE_INFO *) (ListPtr + 1);\r
- ListPtr = ListPtr + 1 + sizeof (EFI_PCI_DEVICE_INFO) / sizeof (UINT64);\r
-\r
- //\r
- // Check whether the PCI device matches the device in the incompatible devices list?\r
- // If not, ship next\r
- //\r
- if (DeviceCheck (PciDeviceInfo, Header) != EFI_SUCCESS) {\r
- continue;\r
- }\r
-\r
- //\r
- // Matched an item, check whether access matches?\r
- //\r
- for (; *ListPtr == DEVICE_RES_TAG;) {\r
- ListPtr ++;\r
- if (((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessType == AccessType &&\r
- ((EFI_PCI_REGISTER_ACCESS_DESCRIPTOR *) ListPtr)->AccessWidth == AccessWidth ) {\r
-\r
- Dsc = (EFI_PCI_REGISTER_ACCESS_DATA *) (ListPtr + 2);\r
-\r
- if((Dsc->StartOffset <= Offset) && (Dsc->EndOffset > Offset)) {\r
-\r
- RegisterPtr = &mPciRegisterAccessData;\r
-\r
- RegisterPtr->StartOffset = Dsc->StartOffset;\r
- RegisterPtr->EndOffset = Dsc->EndOffset;\r
- RegisterPtr->Width = Dsc->Width;\r
-\r
- *(VOID **) Configuration = RegisterPtr;\r
-\r
- return EFI_SUCCESS;\r
- }\r
- }\r
- ListPtr += sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR) / (sizeof (UINT64));\r
- }\r
- return EFI_UNSUPPORTED;\r
-\r
- case DEVICE_RES_TAG:\r
- //\r
- // Adjust the pointer to the next item\r
- //\r
- ListPtr = ListPtr + 1 + ((sizeof (EFI_PCI_REGISTER_ACCESS_DESCRIPTOR)) / sizeof (UINT64));\r
- break;\r
-\r
- default:\r
- return EFI_UNSUPPORTED;\r
- }\r
- }\r
-\r
- return EFI_UNSUPPORTED;\r
-}\r
-\r
+++ /dev/null
-#/** @file\r
-# PCI Incompatible device support Library template.\r
-#\r
-# Check PCI incompatible devices and set necessary configuration.\r
-# Copyright (c) 2007 - 2009, Intel Corporation.\r
-#\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PciIncompatibleDeviceSupportLib\r
- FILE_GUID = 1ca1c1f9-5baf-4204-b6e5-5e24109a4e4e\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PciIncompatibleDeviceSupportLib|DXE_DRIVER UEFI_DRIVER\r
- EFI_SPECIFICATION_VERSION = 0x00020000\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
-#\r
-\r
-[Sources.common]\r
- IncompatiblePciDeviceList.h\r
- PciIncompatibleDeviceSupportLib.c\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
-\r
-[LibraryClasses]\r
- MemoryAllocationLib\r
- DebugLib\r