IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64

[mirror_edk2.git] / IntelFsp2Pkg / FspSecCore / Ia32 / FspApiEntryT.nasm

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 7fd3d6d84315746e6ff12c4fd818a8acb9f04d2a..61030a843b8d887e8505dbe1a469baef5b984413 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -1,7 +1,7 @@
 ;; @file\r
 ;  Provide FSP API entry points.\r
 ;\r
-; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;;\r
 \r
@@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22
     .FspUpdHeaderRevision:    resb    1\r
     .FspUpdHeaderReserved:    resb   23\r
     ; }\r
-    ; FSPT_ARCH_UPD{\r
-    .FsptArchUpd:             resd    8\r
+    ; FSPT_ARCH_UPD {\r
+    .FsptArchRevision:        resb    1\r
+    .FsptArchReserved:        resb    3\r
+    .FsptArchUpd:             resd    7\r
     ; }\r
     ; FSPT_CORE_UPD {\r
     .MicrocodeCodeAddr:       resd    1\r
@@ -96,6 +98,28 @@ struc LoadMicrocodeParamsFsp22
     .size:\r
 endstruc\r
 \r
+struc LoadMicrocodeParamsFsp24\r
+    ; FSP_UPD_HEADER {\r
+    .FspUpdHeaderSignature:   resd    2\r
+    .FspUpdHeaderRevision:    resb    1\r
+    .FspUpdHeaderReserved:    resb   23\r
+    ; }\r
+    ; FSPT_ARCH2_UPD {\r
+    .FsptArchRevision:        resb    1\r
+    .FsptArchReserved:        resb    3\r
+    .FsptArchLength:          resd    1\r
+    .FspDebugHandler          resq    1\r
+    .FsptArchUpd:             resd    4\r
+    ; }\r
+    ; FSPT_CORE_UPD {\r
+    .MicrocodeCodeAddr:       resq    1\r
+    .MicrocodeCodeSize:       resq    1\r
+    .CodeRegionBase:          resq    1\r
+    .CodeRegionSize:          resq    1\r
+    ; }\r
+    .size:\r
+endstruc\r
+\r
 ;\r
 ; Define SSE macros\r
 ;\r
@@ -172,9 +196,9 @@ ASM_PFX(LoadMicrocodeDefault):
    ;   Executed by SBSP and NBSP\r
    ;   Beginning of microcode update region starts on paragraph boundary\r
 \r
-   ;\r
    ;\r
    ; Save return address to EBP\r
+   ;\r
    movd   ebp, mm7\r
 \r
    cmp    esp, 0\r
@@ -188,8 +212,12 @@ ASM_PFX(LoadMicrocodeDefault):
    ; and report error if size is less than 2k\r
    ; first check UPD header revision\r
    cmp    byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
-   jae    Fsp22UpdHeader\r
+   jb     Fsp20UpdHeader\r
+   cmp    byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
+   je     Fsp24UpdHeader\r
+   jmp    Fsp22UpdHeader\r
 \r
+Fsp20UpdHeader:\r
    ; UPD structure is compliant with FSP spec 2.0/2.1\r
    mov    eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
    cmp    eax, 0\r
@@ -213,6 +241,19 @@ Fsp22UpdHeader:
    mov    esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
    cmp    esi, 0\r
    jnz    CheckMainHeader\r
+   jmp    ParamError\r
+\r
+Fsp24UpdHeader:\r
+   ; UPD structure is compliant with FSP spec 2.4\r
+   mov    eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
+   cmp    eax, 0\r
+   jz     Exit2\r
+   cmp    eax, 0800h\r
+   jl     ParamError\r
+\r
+   mov    esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
+   cmp    esi, 0\r
+   jnz    CheckMainHeader\r
 \r
 ParamError:\r
    mov    eax, 080000002h\r
@@ -308,9 +349,13 @@ AdvanceFixedSize:
 \r
 CheckAddress:\r
    ; Check UPD header revision\r
-   cmp    byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
-   jae    Fsp22UpdHeader1\r
+   cmp   byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
+   jb     Fsp20UpdHeader1\r
+   cmp    byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
+   je     Fsp24UpdHeader1;\r
+   jmp    Fsp22UpdHeader1\r
 \r
+Fsp20UpdHeader1:\r
    ; UPD structure is compliant with FSP spec 2.0/2.1\r
    ; Is automatic size detection ?\r
    mov   eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
@@ -336,6 +381,19 @@ Fsp22UpdHeader1:
    jae   Done        ;Jif address is outside of microcode region\r
    jmp   CheckMainHeader\r
 \r
+Fsp24UpdHeader1:\r
+   ; UPD structure is compliant with FSP spec 2.4\r
+   ; Is automatic size detection ?\r
+   mov   eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
+   cmp   eax, 0ffffffffh\r
+   jz    LoadMicrocodeDefault4\r
+\r
+   ; Address >= microcode region address + microcode region size?\r
+   add   eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
+   cmp   esi, eax\r
+   jae   Done        ;Jif address is outside of microcode region\r
+   jmp   CheckMainHeader\r
+\r
 LoadMicrocodeDefault4:\r
    ; Is valid Microcode start point ?\r
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
@@ -351,7 +409,7 @@ LoadCheck:
    mov   eax, 1\r
    cpuid\r
    mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
-   rdmsr                         ; Get current microcode signature\r
+   rdmsr                        ; Get current microcode signature\r
 \r
    ; Verify this microcode update is not already loaded\r
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx\r
@@ -405,8 +463,12 @@ ASM_PFX(EstablishStackFsp):
 \r
   ; check UPD structure revision (edx + 8)\r
   cmp       byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
-  jae       Fsp22UpdHeader2\r
+  jb        Fsp20UpdHeader2\r
+  cmp       byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
+  je        Fsp24UpdHeader2\r
+  jmp       Fsp22UpdHeader2\r
 \r
+Fsp20UpdHeader2:\r
   ; UPD structure is compliant with FSP spec 2.0/2.1\r
   push      dword [edx + LoadMicrocodeParams.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 12\r
   push      dword [edx + LoadMicrocodeParams.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 8\r
@@ -420,6 +482,14 @@ Fsp22UpdHeader2:
   push      dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 8\r
   push      dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 4\r
   push      dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
+  jmp       ContinueAfterUpdPush\r
+\r
+Fsp24UpdHeader2:\r
+  ; UPD structure is compliant with FSP spec 2.4\r
+  push      dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 24\r
+  push      dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 16\r
+  push      dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 8\r
+  push      dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
 \r
 ContinueAfterUpdPush:\r
   ;\r
@@ -517,13 +587,13 @@ ASM_PFX(TempRamInitApi):
   cmp       eax, 0\r
   jnz       TempRamInitExit\r
 \r
-  LXMMN      xmm6, eax, 3  ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r
+  LXMMN     xmm6, eax, 3  ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r
 \r
 TempRamInitExit:\r
-   mov      bl, al                  ; save al data in bl\r
-   mov      al, 07Fh                ; API exit postcode 7f\r
-   out      080h, al\r
-   mov      al, bl                  ; restore al data from bl\r
+  mov       bl, al                  ; save al data in bl\r
+  mov       al, 07Fh                ; API exit postcode 7f\r
+  out       080h, al\r
+  mov       al, bl                  ; restore al data from bl\r
 \r
   ;\r
   ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6\r