IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64

[mirror_edk2.git] / IntelFsp2Pkg / Include / FspGlobalData.h

diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/FspGlobalData.h
index 2a03129f4a19851cb80937ae2de819ba0d7f15e2..445540abfa51b8b7c94e5bb6565d6a5e32db0f85 100644 (file)
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -1,13 +1,7 @@
 /** @file\r
 \r
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php.\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -16,8 +10,9 @@
 \r
 #include <FspEas.h>\r
 \r
-#define FSP_IN_API_MODE      0\r
-#define FSP_IN_DISPATCH_MODE 1\r
+#define FSP_IN_API_MODE         0\r
+#define FSP_IN_DISPATCH_MODE    1\r
+#define FSP_GLOBAL_DATA_VERSION 1\r
 \r
 #pragma pack(1)\r
 \r
@@ -28,42 +23,75 @@ typedef enum {
   FspMemoryInitApiIndex,\r
   TempRamExitApiIndex,\r
   FspSiliconInitApiIndex,\r
+  FspMultiPhaseSiInitApiIndex,\r
   FspApiIndexMax\r
 } FSP_API_INDEX;\r
 \r
 typedef struct  {\r
-   VOID               *DataPtr;\r
-   UINT32             MicrocodeRegionBase;\r
-   UINT32             MicrocodeRegionSize;\r
-   UINT32             CodeRegionBase;\r
-   UINT32             CodeRegionSize;\r
+  VOID      *DataPtr;\r
+  UINTN     MicrocodeRegionBase;\r
+  UINTN     MicrocodeRegionSize;\r
+  UINTN     CodeRegionBase;\r
+  UINTN     CodeRegionSize;\r
+  UINTN     Reserved;\r
 } FSP_PLAT_DATA;\r
 \r
-#define FSP_GLOBAL_DATA_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'D')\r
-#define FSP_PERFORMANCE_DATA_SIGNATURE  SIGNATURE_32 ('P', 'E', 'R', 'F')\r
-#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF\r
+#define FSP_GLOBAL_DATA_SIGNATURE        SIGNATURE_32 ('F', 'S', 'P', 'D')\r
+#define FSP_PERFORMANCE_DATA_SIGNATURE   SIGNATURE_32 ('P', 'E', 'R', 'F')\r
+#define FSP_PERFORMANCE_DATA_TIMER_MASK  0xFFFFFFFFFFFFFF\r
 \r
 typedef struct  {\r
-   UINT32             Signature;\r
-   UINT8              Version;\r
-   UINT8              Reserved1[3];\r
-   UINT32             CoreStack;\r
-   UINT32             StatusCode;\r
-   UINT32             Reserved2[8];\r
-   FSP_PLAT_DATA      PlatformData;\r
-   FSP_INFO_HEADER    *FspInfoHeader;\r
-   VOID               *UpdDataPtr;\r
-   VOID               *TempRamInitUpdPtr;\r
-   VOID               *MemoryInitUpdPtr;\r
-   VOID               *SiliconInitUpdPtr;\r
-   UINT8              ApiIdx;\r
-   UINT8              FspMode; // 0: FSP in API mode; 1: FSP in DISPATCH mode\r
-   UINT8              Reserved3[30];\r
-   UINT32             PerfSig;\r
-   UINT16             PerfLen;\r
-   UINT16             Reserved4;\r
-   UINT32             PerfIdx;\r
-   UINT64             PerfData[32];\r
+  UINT32             Signature;\r
+  UINT8              Version;\r
+  UINT8              Reserved1[3];\r
+  ///\r
+  /// Offset 0x08\r
+  ///\r
+  UINTN              CoreStack;\r
+  UINTN              Reserved2;\r
+  ///\r
+  /// IA32: Offset 0x10; X64: Offset 0x18\r
+  ///\r
+  UINT32             StatusCode;\r
+  UINT8              ApiIdx;\r
+  ///\r
+  /// 0: FSP in API mode; 1: FSP in DISPATCH mode\r
+  ///\r
+  UINT8              FspMode;\r
+  UINT8              OnSeparateStack;\r
+  UINT8              Reserved3;\r
+  UINT32             NumberOfPhases;\r
+  UINT32             PhasesExecuted;\r
+  UINT32             Reserved4[8];\r
+  ///\r
+  /// IA32: Offset 0x40; X64: Offset 0x48\r
+  /// Start of UINTN and pointer section\r
+  /// All UINTN and pointer members must be put in this section\r
+  /// except CoreStack and Reserved2. In addition, the number of\r
+  /// UINTN and pointer members must be even for natural alignment\r
+  /// in both IA32 and X64.\r
+  ///\r
+  FSP_PLAT_DATA      PlatformData;\r
+  VOID               *TempRamInitUpdPtr;\r
+  VOID               *MemoryInitUpdPtr;\r
+  VOID               *SiliconInitUpdPtr;\r
+  ///\r
+  /// IA32: Offset 0x64; X64: Offset 0x90\r
+  /// To store function parameters pointer\r
+  /// so it can be retrieved after stack switched.\r
+  ///\r
+  VOID               *FunctionParameterPtr;\r
+  FSP_INFO_HEADER    *FspInfoHeader;\r
+  VOID               *UpdDataPtr;\r
+  ///\r
+  /// End of UINTN and pointer section\r
+  ///\r
+  UINT8              Reserved5[16];\r
+  UINT32             PerfSig;\r
+  UINT16             PerfLen;\r
+  UINT16             Reserved6;\r
+  UINT32             PerfIdx;\r
+  UINT64             PerfData[32];\r
 } FSP_GLOBAL_DATA;\r
 \r
 #pragma pack()\r