IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support.

[mirror_edk2.git] / IntelFsp2Pkg / Include / FspGlobalData.h

diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/FspGlobalData.h
index 71033121c4cba3919bf30ede42932ed12247e7c6..697b20ed4ce3febf2d0c581570472f34614d26db 100644 (file)
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -1,6 +1,6 @@
 /** @file\r
 \r
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -10,8 +10,9 @@
 \r
 #include <FspEas.h>\r
 \r
-#define FSP_IN_API_MODE       0\r
-#define FSP_IN_DISPATCH_MODE  1\r
+#define FSP_IN_API_MODE          0\r
+#define FSP_IN_DISPATCH_MODE     1\r
+#define FSP_GLOBAL_DATA_VERSION  1\r
 \r
 #pragma pack(1)\r
 \r
@@ -23,15 +24,17 @@ typedef enum {
   TempRamExitApiIndex,\r
   FspSiliconInitApiIndex,\r
   FspMultiPhaseSiInitApiIndex,\r
+  FspSmmInitApiIndex,\r
   FspApiIndexMax\r
 } FSP_API_INDEX;\r
 \r
 typedef struct  {\r
-  VOID      *DataPtr;\r
-  UINT32    MicrocodeRegionBase;\r
-  UINT32    MicrocodeRegionSize;\r
-  UINT32    CodeRegionBase;\r
-  UINT32    CodeRegionSize;\r
+  VOID     *DataPtr;\r
+  UINTN    MicrocodeRegionBase;\r
+  UINTN    MicrocodeRegionSize;\r
+  UINTN    CodeRegionBase;\r
+  UINTN    CodeRegionSize;\r
+  UINTN    Reserved;\r
 } FSP_PLAT_DATA;\r
 \r
 #define FSP_GLOBAL_DATA_SIGNATURE        SIGNATURE_32 ('F', 'S', 'P', 'D')\r
@@ -39,36 +42,57 @@ typedef struct  {
 #define FSP_PERFORMANCE_DATA_TIMER_MASK  0xFFFFFFFFFFFFFF\r
 \r
 typedef struct  {\r
-  UINT32             Signature;\r
-  UINT8              Version;\r
-  UINT8              Reserved1[3];\r
-  UINT32             CoreStack;\r
-  UINT32             StatusCode;\r
-  UINT32             Reserved2[8];\r
+  UINT32    Signature;\r
+  UINT8     Version;\r
+  UINT8     Reserved1[3];\r
+  ///\r
+  /// Offset 0x08\r
+  ///\r
+  UINTN     CoreStack;\r
+  UINTN     Reserved2;\r
+  ///\r
+  /// IA32: Offset 0x10; X64: Offset 0x18\r
+  ///\r
+  UINT32    StatusCode;\r
+  UINT8     ApiIdx;\r
+  ///\r
+  /// 0: FSP in API mode; 1: FSP in DISPATCH mode\r
+  ///\r
+  UINT8     FspMode;\r
+  UINT8     OnSeparateStack;\r
+  UINT8     Reserved3;\r
+  UINT32    NumberOfPhases;\r
+  UINT32    PhasesExecuted;\r
+  UINT32    Reserved4[8];\r
+  ///\r
+  /// IA32: Offset 0x40; X64: Offset 0x48\r
+  /// Start of UINTN and pointer section\r
+  /// All UINTN and pointer members must be put in this section\r
+  /// except CoreStack and Reserved2. In addition, the number of\r
+  /// UINTN and pointer members must be even for natural alignment\r
+  /// in both IA32 and X64.\r
+  ///\r
   FSP_PLAT_DATA      PlatformData;\r
-  FSP_INFO_HEADER    *FspInfoHeader;\r
-  VOID               *UpdDataPtr;\r
   VOID               *TempRamInitUpdPtr;\r
   VOID               *MemoryInitUpdPtr;\r
   VOID               *SiliconInitUpdPtr;\r
-  UINT8              ApiIdx;\r
-  ///\r
-  /// 0: FSP in API mode; 1: FSP in DISPATCH mode\r
-  ///\r
-  UINT8              FspMode;\r
-  UINT8              OnSeparateStack;\r
-  UINT8              Reserved3;\r
-  UINT32             NumberOfPhases;\r
-  UINT32             PhasesExecuted;\r
+  VOID               *SmmInitUpdPtr;\r
   ///\r
+  /// IA32: Offset 0x68; X64: Offset 0x98\r
   /// To store function parameters pointer\r
   /// so it can be retrieved after stack switched.\r
   ///\r
   VOID               *FunctionParameterPtr;\r
-  UINT8              Reserved4[16];\r
+  FSP_INFO_HEADER    *FspInfoHeader;\r
+  VOID               *UpdDataPtr;\r
+  UINTN              Reserved5;\r
+  ///\r
+  /// End of UINTN and pointer section\r
+  ///\r
+  UINT8              Reserved6[16];\r
   UINT32             PerfSig;\r
   UINT16             PerfLen;\r
-  UINT16             Reserved5;\r
+  UINT16             Reserved7;\r
   UINT32             PerfIdx;\r
   UINT64             PerfData[32];\r
 } FSP_GLOBAL_DATA;\r