--- /dev/null
+## @file\r
+# Sec Core for FSP\r
+#\r
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = FspSecCoreI\r
+ FILE_GUID = 558782b5-782d-415e-ab9e-0ceb79dc3425\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources]\r
+ SecFspApiChk.c\r
+ SecFsp.h\r
+\r
+[Sources.X64]\r
+ X64/FspApiEntryI.nasm\r
+ X64/FspApiEntryCommon.nasm\r
+ X64/FspHelper.nasm\r
+\r
+[Sources.IA32]\r
+ Ia32/FspApiEntryI.nasm\r
+ Ia32/FspApiEntryCommon.nasm\r
+ Ia32/FspHelper.nasm\r
+\r
+[Binaries.Ia32]\r
+ RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ IntelFsp2Pkg/IntelFsp2Pkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseMemoryLib\r
+ DebugLib\r
+ BaseLib\r
+ PciCf8Lib\r
+ SerialPortLib\r
+ FspSwitchStackLib\r
+ FspCommonLib\r
+ FspSecPlatformLib\r
+\r
+\r
--- /dev/null
+;; @file\r
+; Provide FSP API entry points.\r
+;\r
+; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;;\r
+\r
+ SECTION .text\r
+\r
+;\r
+; Following functions will be provided in C\r
+;\r
+extern ASM_PFX(FspApiCommon)\r
+\r
+;----------------------------------------------------------------------------\r
+; FspApiCommonContinue API\r
+;\r
+; This is the FSP API common entry point to resume the FSP execution\r
+;\r
+;----------------------------------------------------------------------------\r
+global ASM_PFX(FspApiCommonContinue)\r
+ASM_PFX(FspApiCommonContinue):\r
+ jmp $\r
+\r
+;----------------------------------------------------------------------------\r
+; FspSmmInit API\r
+;\r
+; This FSP API will notify the FSP about the different phases in the boot\r
+; process\r
+;\r
+;----------------------------------------------------------------------------\r
+global ASM_PFX(FspSmmInitApi)\r
+ASM_PFX(FspSmmInitApi):\r
+ mov eax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex\r
+ jmp ASM_PFX(FspApiCommon)\r
+\r
+;----------------------------------------------------------------------------\r
+; Module Entrypoint API\r
+;----------------------------------------------------------------------------\r
+global ASM_PFX(_ModuleEntryPoint)\r
+ASM_PFX(_ModuleEntryPoint):\r
+ jmp $\r
+ ; Add reference to APIs so that it will not be optimized by compiler\r
+ jmp ASM_PFX(FspSmmInitApi)\r
Status = EFI_INVALID_PARAMETER;\r
}\r
}\r
+ } else if (ApiIdx == FspSmmInitApiIndex) {\r
+ //\r
+ // FspSmmInitApiIndex check\r
+ //\r
+ if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS) || ((UINTN)FspData == MAX_UINT32)) {\r
+ Status = EFI_UNSUPPORTED;\r
+ } else {\r
+ if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {\r
+ Status = EFI_UNSUPPORTED;\r
+ } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiParam))) {\r
+ Status = EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
} else {\r
Status = EFI_UNSUPPORTED;\r
}\r
;----------------------------------------------------------------------------\r
global ASM_PFX(NotifyPhaseApi)\r
ASM_PFX(NotifyPhaseApi):\r
- mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex\r
+ mov rax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex\r
jmp ASM_PFX(FspApiCommon)\r
\r
;----------------------------------------------------------------------------\r
;----------------------------------------------------------------------------\r
global ASM_PFX(FspSiliconInitApi)\r
ASM_PFX(FspSiliconInitApi):\r
- mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex\r
+ mov rax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex\r
jmp ASM_PFX(FspApiCommon)\r
\r
;----------------------------------------------------------------------------\r
\r
global ASM_PFX(FspMultiPhaseSiInitApi)\r
ASM_PFX(FspMultiPhaseSiInitApi):\r
- mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex\r
+ mov rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex\r
jmp ASM_PFX(FspApiCommon)\r
\r
;----------------------------------------------------------------------------\r
;\r
; Handle FspMultiPhaseSiInitApiIndex API\r
;\r
- cmp eax, 6\r
+ cmp rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex\r
jnz NotMultiPhaseSiInitApi\r
\r
PUSHA_64\r
--- /dev/null
+;; @file\r
+; Provide FSP API entry points.\r
+;\r
+; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;;\r
+\r
+ SECTION .text\r
+\r
+;\r
+; Following functions will be provided in C\r
+;\r
+extern ASM_PFX(FspApiCommon)\r
+\r
+;----------------------------------------------------------------------------\r
+; FspApiCommonContinue API\r
+;\r
+; This is the FSP API common entry point to resume the FSP execution\r
+;\r
+;----------------------------------------------------------------------------\r
+global ASM_PFX(FspApiCommonContinue)\r
+ASM_PFX(FspApiCommonContinue):\r
+ jmp $\r
+\r
+;----------------------------------------------------------------------------\r
+; FspSmmInit API\r
+;\r
+; This FSP API will notify the FSP about the different phases in the boot\r
+; process\r
+;\r
+;----------------------------------------------------------------------------\r
+global ASM_PFX(FspSmmInitApi)\r
+ASM_PFX(FspSmmInitApi):\r
+ mov rax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex\r
+ jmp ASM_PFX(FspApiCommon)\r
+\r
+;----------------------------------------------------------------------------\r
+; Module Entrypoint API\r
+;----------------------------------------------------------------------------\r
+global ASM_PFX(_ModuleEntryPoint)\r
+ASM_PFX(_ModuleEntryPoint):\r
+ jmp $\r
+ ; Add reference to APIs so that it will not be optimized by compiler\r
+ jmp ASM_PFX(FspSmmInitApi)\r
;----------------------------------------------------------------------------\r
global ASM_PFX(FspMemoryInitApi)\r
ASM_PFX(FspMemoryInitApi):\r
- mov eax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex\r
+ mov rax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex\r
jmp ASM_PFX(FspApiCommon)\r
\r
;----------------------------------------------------------------------------\r
;----------------------------------------------------------------------------\r
global ASM_PFX(TempRamExitApi)\r
ASM_PFX(TempRamExitApi):\r
- mov eax, 4 ; FSP_API_INDEX.TempRamExitApiIndex\r
+ mov rax, 4 ; FSP_API_INDEX.TempRamExitApiIndex\r
jmp ASM_PFX(FspApiCommon)\r
\r
;----------------------------------------------------------------------------\r
;----------------------------------------------------------------------------\r
global ASM_PFX(NotifyPhaseApi)\r
ASM_PFX(NotifyPhaseApi):\r
- mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex\r
+ mov rax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex\r
jmp ASM_PFX(FspApiCommon)\r
\r
;----------------------------------------------------------------------------\r
;----------------------------------------------------------------------------\r
global ASM_PFX(FspSiliconInitApi)\r
ASM_PFX(FspSiliconInitApi):\r
- mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex\r
+ mov rax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex\r
jmp ASM_PFX(FspApiCommon)\r
\r
;----------------------------------------------------------------------------\r
IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr\r
);\r
\r
+/**\r
+ This FSP API initializes SMM and provide any OS runtime silicon services,\r
+ including Reliability, Availability, and Serviceability (RAS) features implemented by the CPU.\r
+\r
+ @param[in] FspiUpdDataPtr Pointer to the FSPI_UPD data structure.\r
+ If NULL, FSP will use the default parameters.\r
+\r
+ @retval EFI_SUCCESS FSP execution environment was initialized successfully.\r
+ @retval EFI_INVALID_PARAMETER Input parameters are invalid.\r
+ @retval EFI_UNSUPPORTED The FSP calling conditions were not met.\r
+ @retval EFI_DEVICE_ERROR FSP initialization failed.\r
+ @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *FSP_SMM_INIT)(\r
+ IN VOID *FspiUpdDataPtr\r
+ );\r
+\r
#endif\r
\r
#include <FspEas.h>\r
\r
-#define FSP_IN_API_MODE 0\r
-#define FSP_IN_DISPATCH_MODE 1\r
-#define FSP_GLOBAL_DATA_VERSION 1\r
+#define FSP_IN_API_MODE 0\r
+#define FSP_IN_DISPATCH_MODE 1\r
+#define FSP_GLOBAL_DATA_VERSION 1\r
\r
#pragma pack(1)\r
\r
TempRamExitApiIndex,\r
FspSiliconInitApiIndex,\r
FspMultiPhaseSiInitApiIndex,\r
+ FspSmmInitApiIndex,\r
FspApiIndexMax\r
} FSP_API_INDEX;\r
\r
typedef struct {\r
- VOID *DataPtr;\r
- UINTN MicrocodeRegionBase;\r
- UINTN MicrocodeRegionSize;\r
- UINTN CodeRegionBase;\r
- UINTN CodeRegionSize;\r
- UINTN Reserved;\r
+ VOID *DataPtr;\r
+ UINTN MicrocodeRegionBase;\r
+ UINTN MicrocodeRegionSize;\r
+ UINTN CodeRegionBase;\r
+ UINTN CodeRegionSize;\r
+ UINTN Reserved;\r
} FSP_PLAT_DATA;\r
\r
#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')\r
#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF\r
\r
typedef struct {\r
- UINT32 Signature;\r
- UINT8 Version;\r
- UINT8 Reserved1[3];\r
+ UINT32 Signature;\r
+ UINT8 Version;\r
+ UINT8 Reserved1[3];\r
///\r
/// Offset 0x08\r
///\r
- UINTN CoreStack;\r
- UINTN Reserved2;\r
+ UINTN CoreStack;\r
+ UINTN Reserved2;\r
///\r
/// IA32: Offset 0x10; X64: Offset 0x18\r
///\r
- UINT32 StatusCode;\r
- UINT8 ApiIdx;\r
+ UINT32 StatusCode;\r
+ UINT8 ApiIdx;\r
///\r
/// 0: FSP in API mode; 1: FSP in DISPATCH mode\r
///\r
- UINT8 FspMode;\r
- UINT8 OnSeparateStack;\r
- UINT8 Reserved3;\r
- UINT32 NumberOfPhases;\r
- UINT32 PhasesExecuted;\r
- UINT32 Reserved4[8];\r
+ UINT8 FspMode;\r
+ UINT8 OnSeparateStack;\r
+ UINT8 Reserved3;\r
+ UINT32 NumberOfPhases;\r
+ UINT32 PhasesExecuted;\r
+ UINT32 Reserved4[8];\r
///\r
/// IA32: Offset 0x40; X64: Offset 0x48\r
/// Start of UINTN and pointer section\r
VOID *TempRamInitUpdPtr;\r
VOID *MemoryInitUpdPtr;\r
VOID *SiliconInitUpdPtr;\r
+ VOID *SmmInitUpdPtr;\r
///\r
- /// IA32: Offset 0x64; X64: Offset 0x90\r
+ /// IA32: Offset 0x68; X64: Offset 0x98\r
/// To store function parameters pointer\r
/// so it can be retrieved after stack switched.\r
///\r
VOID *FunctionParameterPtr;\r
FSP_INFO_HEADER *FspInfoHeader;\r
VOID *UpdDataPtr;\r
+ UINTN Reserved5;\r
///\r
/// End of UINTN and pointer section\r
///\r
- UINT8 Reserved5[16];\r
+ UINT8 Reserved6[16];\r
UINT32 PerfSig;\r
UINT16 PerfLen;\r
- UINT16 Reserved6;\r
+ UINT16 Reserved7;\r
UINT32 PerfIdx;\r
UINT64 PerfData[32];\r
} FSP_GLOBAL_DATA;\r
\r
#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')\r
\r
-#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0\r
-#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1\r
-#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2\r
-#define FSP_IA32 0\r
-#define FSP_X64 1\r
+#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0\r
+#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1\r
+#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2\r
+#define FSP_IA32 0\r
+#define FSP_X64 1\r
\r
-#pragma pack(1)\r
+ #pragma pack(1)\r
\r
///\r
/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.\r
/// Byte 0x4E: Reserved4.\r
///\r
UINT16 Reserved4;\r
+ ///\r
+ /// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.\r
+ ///\r
+ UINT32 FspMultiPhaseMemInitEntryOffset;\r
+ ///\r
+ /// Byte 0x54: Offset for the API to initialize SMM.\r
+ ///\r
+ UINT32 FspSmmInitEntryOffset;\r
} FSP_INFO_HEADER;\r
\r
///\r
// UINT32 PatchData[];\r
} FSP_PATCH_TABLE;\r
\r
-#pragma pack()\r
+ #pragma pack()\r
\r
extern EFI_GUID gFspHeaderFileGuid;\r
\r
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf\r
IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf\r
IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf\r
+ IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf\r
IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf\r
IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf\r
\r
return NoFileChange\r
\r
def CreateSplitUpdTxt (self, UpdTxtFile):\r
- GuidList = ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_UPD_TOOL_GUID']\r
- SignatureList = ['0x545F', '0x4D5F','0x535F'] # _T, _M, and _S signature for FSPT, FSPM, FSPS\r
+ GuidList = ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_UPD_TOOL_GUID','FSP_I_UPD_TOOL_GUID']\r
+ SignatureList = ['0x545F', '0x4D5F','0x535F','0x495F'] # _T, _M, _S and _I signature for FSPT, FSPM, FSPS, FSPI\r
for Index in range(len(GuidList)):\r
UpdTxtFile = ''\r
FvDir = self._FvDir\r
Chars.append(chr(Value & 0xFF))\r
Value = Value >> 8\r
SignatureStr = ''.join(Chars)\r
- # Signature will be _T / _M / _S for FSPT / FSPM / FSPS accordingly\r
+ # Signature will be _T / _M / _S / _I for FSPT / FSPM / FSPS /FSPI accordingly\r
if '_T' in SignatureStr[6:6+2]:\r
TxtBody.append("#define FSPT_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr))\r
elif '_M' in SignatureStr[6:6+2]:\r
TxtBody.append("#define FSPM_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr))\r
elif '_S' in SignatureStr[6:6+2]:\r
TxtBody.append("#define FSPS_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr))\r
+ elif '_I' in SignatureStr[6:6+2]:\r
+ TxtBody.append("#define FSPI_UPD_SIGNATURE %s /* '%s' */\n\n" % (Item['value'], SignatureStr))\r
TxtBody.append("\n")\r
\r
for Region in ['UPD']:\r
UpdOffsetTable = []\r
- UpdSignature = ['0x545F', '0x4D5F', '0x535F'] #['_T', '_M', '_S'] signature for FSPT, FSPM, FSPS\r
- UpdStructure = ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD']\r
+ UpdSignature = ['0x545F', '0x4D5F', '0x535F', '0x495F'] #['_T', '_M', '_S', '_I'] signature for FSPT, FSPM, FSPS, FSPI\r
+ UpdStructure = ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD', 'FSPI_UPD']\r
for Item in self._CfgItemList:\r
if Item["cname"] == 'Signature' and Item["value"][0:6] in UpdSignature:\r
Item["offset"] = 0 # re-initialize offset to 0 when new UPD structure starting\r
HeaderTFileName = 'FsptUpd.h'\r
HeaderMFileName = 'FspmUpd.h'\r
HeaderSFileName = 'FspsUpd.h'\r
+ HeaderIFileName = 'FspiUpd.h'\r
\r
- UpdRegionCheck = ['FSPT', 'FSPM', 'FSPS'] # FSPX_UPD_REGION\r
- UpdConfigCheck = ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG\r
- UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE']\r
- ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_ARCH_UPD']\r
+ UpdRegionCheck = ['FSPT', 'FSPM', 'FSPS', 'FSPI'] # FSPX_UPD_REGION\r
+ UpdConfigCheck = ['FSP_T', 'FSP_M', 'FSP_S', 'FSP_I'] # FSP_X_CONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG\r
+ UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE', 'FSPI_UPD_SIGNATURE']\r
+ ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_ARCH_UPD', 'FSPI_ARCH_UPD']\r
ExcludedSpecificUpd1 = ['FSPT_ARCH2_UPD', 'FSPM_ARCH2_UPD', 'FSPS_ARCH2_UPD']\r
\r
IncLines = []\r
elif UpdRegionCheck[item] == 'FSPS':\r
HeaderFd = open(os.path.join(FvDir, HeaderSFileName), "w")\r
FileBase = os.path.basename(os.path.join(FvDir, HeaderSFileName))\r
+ elif UpdRegionCheck[item] == 'FSPI':\r
+ HeaderFd = open(os.path.join(FvDir, HeaderIFileName), "w")\r
+ FileBase = os.path.basename(os.path.join(FvDir, HeaderIFileName))\r
FileName = FileBase.replace(".", "_").upper()\r
HeaderFd.write("%s\n" % (__copyright_h__ % date.today().year))\r
HeaderFd.write("#ifndef __%s__\n" % FileName)\r
\r
\r
def Usage():\r
- print ("GenCfgOpt Version 0.57")\r
+ print ("GenCfgOpt Version 0.58")\r
print ("Usage:")\r
print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir [-D Macros]")\r
print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile [-D Macros]")\r
## @ SplitFspBin.py\r
#\r
-# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
self.FihOffset = fihoff\r
self.Offset = offset\r
self.FvIdxList = []\r
- self.Type = "XTMSXXXXOXXXXXXX"[(fih.ComponentAttribute >> 12) & 0x0F]\r
+ self.Type = "XTMSIXXXXOXXXXXXX"[(fih.ComponentAttribute >> 12) & 0x0F]\r
self.PatchList = patch\r
self.PatchList.append(fihoff + 0x1C)\r
\r
parser_rebase = subparsers.add_parser('rebase', help='rebase a FSP into a new base address')\r
parser_rebase.set_defaults(which='rebase')\r
parser_rebase.add_argument('-f', '--fspbin' , dest='FspBinary', type=str, help='FSP binary file path', required = True)\r
- parser_rebase.add_argument('-c', '--fspcomp', choices=['t','m','s','o'], nargs='+', dest='FspComponent', type=str, help='FSP component to rebase', default = "['t']", required = True)\r
+ parser_rebase.add_argument('-c', '--fspcomp', choices=['t','m','s','o','i'], nargs='+', dest='FspComponent', type=str, help='FSP component to rebase', default = "['t']", required = True)\r
parser_rebase.add_argument('-b', '--newbase', dest='FspBase', nargs='+', type=str, help='Rebased FSP binary file name', default = '', required = True)\r
parser_rebase.add_argument('-o', '--outdir' , dest='OutputDir', type=str, help='Output directory path', default = '.')\r
parser_rebase.add_argument('-n', '--outfile', dest='OutputFile', type=str, help='Rebased FSP binary file name', default = '')\r
projects / mirror_edk2.git / commitdiff