#\r
# GUID defined in package\r
#\r
- gFspWrapperTokenSpaceGuid = { 0xa34cf082, 0xf50, 0x4f0d, { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }\r
+ gIntelFsp2WrapperTokenSpaceGuid = { 0xa34cf082, 0xf50, 0x4f0d, { 0x89, 0x8a, 0x3d, 0x39, 0x30, 0x2b, 0xc5, 0x1e } }\r
gFspApiPerformanceGuid = { 0xc9122295, 0x56ed, 0x4d4e, { 0x06, 0xa6, 0x50, 0x8d, 0x89, 0x4d, 0x3e, 0x40 } }\r
gFspHobGuid = { 0x6d86fb36, 0xba90, 0x472c, { 0xb5, 0x83, 0x3f, 0xbe, 0xd3, 0xfb, 0x20, 0x9a } }\r
\r
################################################################################\r
[PcdsFixedAtBuild, PcdsPatchableInModule]\r
## Provides the memory mapped base address of the BIOS CodeCache Flash Device.\r
- gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFE00000|UINT32|0x10000001\r
## Provides the size of the BIOS Flash Device.\r
- gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002\r
\r
## Indicates the base address of the first Microcode Patch in the Microcode Region\r
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005\r
- gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x10000006\r
## Indicates the offset of the Cpu Microcode.\r
- gFspWrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10000007\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset|0x90|UINT32|0x10000007\r
\r
## Indicate the PEI memory size platform want to report\r
- gFspWrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x1800000|UINT32|0x40000004\r
## Indicate the PEI memory size platform want to report\r
- gFspWrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT32|0x40000005\r
\r
## This is the base address of FSP-T/M/S\r
- gFspWrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300\r
- gFspWrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00000301\r
- gFspWrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00000302\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x00000300\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0x00000301\r
+\r
+ ## This PCD indicates if FSP APIs are skipped from FSP wrapper.<BR><BR>\r
+ # If a bit is set, that means this FSP API is skipped.<BR>\r
+ # If a bit is clear, that means this FSP API is NOT skipped.<BR>\r
+ # NOTE: Only NotifyPhase Post PCI enumeration (BIT16) is implemented.<BR>\r
+ # BIT[15:0] is for function:<BR>\r
+ # BIT0 - Skip TempRamInit<BR>\r
+ # BIT1 - Skip MemoryInit<BR>\r
+ # BIT2 - Skip TempRamExit<BR>\r
+ # BIT3 - Skip SiliconInit<BR>\r
+ # BIT4 - Skip NotifyPhase<BR>\r
+ # BIT[32:16] is for sub-function:<BR>\r
+ # BIT16 - Skip NotifyPhase (AfterPciEnumeration)<BR>\r
+ # BIT17 - Skip NotifyPhase (ReadyToBoot)<BR>\r
+ # BIT18 - Skip NotifyPhase (EndOfFirmware)<BR>\r
+ # Any undefined BITs are reserved for future use.<BR>\r
+ # @Prompt Skip FSP API from FSP wrapper.\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000009\r
+\r
+[PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]\r
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001\r
+
\ No newline at end of file