/** @file\r
Header file for AHCI mode of ATA host controller.\r
- \r
- Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
#ifndef __ATA_HC_AHCI_MODE_H__\r
#define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000\r
\r
#define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device\r
-#define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20 \r
+#define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20\r
#define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host\r
#define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20\r
#define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host\r
#define EFI_AHCI_PORT_IS 0x0010\r
#define EFI_AHCI_PORT_IS_DHRS BIT0\r
#define EFI_AHCI_PORT_IS_PSS BIT1\r
-#define EFI_AHCI_PORT_IS_SSS BIT2\r
+#define EFI_AHCI_PORT_IS_DSS BIT2\r
#define EFI_AHCI_PORT_IS_SDBS BIT3\r
#define EFI_AHCI_PORT_IS_UFS BIT4\r
#define EFI_AHCI_PORT_IS_DPS BIT5\r
#define EFI_AHCI_PORT_IS_CPDS BIT31\r
#define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF\r
#define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F\r
+#define EFI_AHCI_PORT_IS_ERROR_MASK (EFI_AHCI_PORT_IS_INFS | EFI_AHCI_PORT_IS_IFS | EFI_AHCI_PORT_IS_HBDS | EFI_AHCI_PORT_IS_HBFS | EFI_AHCI_PORT_IS_TFES)\r
+#define EFI_AHCI_PORT_IS_FATAL_ERROR_MASK (EFI_AHCI_PORT_IS_IFS | EFI_AHCI_PORT_IS_HBDS | EFI_AHCI_PORT_IS_HBFS | EFI_AHCI_PORT_IS_TFES)\r
\r
#define EFI_AHCI_PORT_IE 0x0014\r
#define EFI_AHCI_PORT_CMD 0x0018\r
#define EFI_AHCI_PORT_CMD_SUD BIT1\r
#define EFI_AHCI_PORT_CMD_POD BIT2\r
#define EFI_AHCI_PORT_CMD_CLO BIT3\r
-#define EFI_AHCI_PORT_CMD_CR BIT15\r
#define EFI_AHCI_PORT_CMD_FRE BIT4\r
+#define EFI_AHCI_PORT_CMD_CCS_MASK (BIT8 | BIT9 | BIT10 | BIT11 | BIT12)\r
+#define EFI_AHCI_PORT_CMD_CCS_SHIFT 8\r
#define EFI_AHCI_PORT_CMD_FR BIT14\r
+#define EFI_AHCI_PORT_CMD_CR BIT15\r
#define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)\r
#define EFI_AHCI_PORT_CMD_PMA BIT17\r
#define EFI_AHCI_PORT_CMD_HPCP BIT18\r
UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count\r
UINT32 AhciCmdCtba; //Command Table Descriptor Base Address\r
UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs\r
- UINT32 AhciCmdRsvd1[4]; \r
+ UINT32 AhciCmdRsvd1[4];\r
} EFI_AHCI_COMMAND_LIST;\r
\r
//\r
// This is a software constructed FIS.\r
-// For data transfer operations, this is the H2D Register FIS format as \r
+// For data transfer operations, this is the H2D Register FIS format as\r
// specified in the Serial ATA Revision 2.6 specification.\r
//\r
typedef struct {\r
UINT8 AhciCFisRsvd5[44];\r
} EFI_AHCI_COMMAND_FIS;\r
\r
+typedef enum {\r
+ SataFisD2H = 0,\r
+ SataFisPioSetup,\r
+ SataFisDmaSetup\r
+} SATA_FIS_TYPE;\r
+\r
//\r
// ACMD: ATAPI command (12 or 16 bytes)\r
//\r
// Physical Region Descriptor Table includes up to 65535 entries\r
// The entry data structure is listed at the following.\r
// the actual entry number comes from the PRDTL field in the command\r
-// list entry for this command slot. \r
+// list entry for this command slot.\r
//\r
typedef struct {\r
UINT32 AhciPrdtDba; //Data Base Address\r
} EFI_AHCI_COMMAND_PRDT;\r
\r
//\r
-// Command table data strucute which is pointed to by the entry in the command list\r
+// Command table data structure which is pointed to by the entry in the command list\r
//\r
typedef struct {\r
EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.\r
UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00\r
UINT8 AhciDmaSetupFisRsvd[0x04];\r
UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20\r
- UINT8 AhciPioSetupFisRsvd[0x0C]; \r
+ UINT8 AhciPioSetupFisRsvd[0x0C];\r
UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40\r
UINT8 AhciD2HRegisterFisRsvd[0x04];\r
UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58\r
- UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60\r
- UINT8 AhciUnknownFisRsvd[0x60]; \r
-} EFI_AHCI_RECEIVED_FIS; \r
+ UINT8 AhciUnknownFis[0x40]; // Unknown Fis: offset 0x60\r
+ UINT8 AhciUnknownFisRsvd[0x60];\r
+} EFI_AHCI_RECEIVED_FIS;\r
\r
typedef struct {\r
UINT8 Madt : 5;\r
} EFI_AHCI_REGISTERS;\r
\r
/**\r
- This function is used to send out ATAPI commands conforms to the Packet Command \r
+ This function is used to send out ATAPI commands conforms to the Packet Command\r
with PIO Protocol.\r
\r
@param PciIo The PCI IO protocol instance.\r
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.\r
- @param Port The number of port. \r
+ @param Port The number of port.\r
@param PortMultiplier The number of port multiplier.\r
@param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.\r
\r
\r
/**\r
Start command for give slot on specific port.\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
@param CommandSlot The number of CommandSlot.\r
@param Timeout The timeout value of start, uses 100ns as a unit.\r
- \r
+\r
@retval EFI_DEVICE_ERROR The command start unsuccessfully.\r
@retval EFI_TIMEOUT The operation is time out.\r
@retval EFI_SUCCESS The command start successfully.\r
\r
/**\r
Stop command running for giving port\r
- \r
+\r
@param PciIo The PCI IO protocol instance.\r
@param Port The number of port.\r
@param Timeout The timeout value of stop, uses 100ns as a unit.\r
- \r
+\r
@retval EFI_DEVICE_ERROR The command stop unsuccessfully.\r
@retval EFI_TIMEOUT The operation is time out.\r
@retval EFI_SUCCESS The command stop successfully.\r
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