MdeModulePkg/SdMmcPciHcDxe Fix eMMC HS400 switch sequence

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.c

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
index 3a6ed02be77c72cbbd0202871c50e1e22b5abfc9..11c36132fd4f77a57b6f4cc4926c7e931a04bdc9 100644 (file)
--- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
@@ -2,7 +2,7 @@
 \r
   The EHCI register operation routines.\r
 \r
-Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -65,7 +65,7 @@ EhcReadCapRegister (
 **/\r
 UINT32\r
 EhcReadDbgRegister (\r
-  IN  USB2_HC_DEV         *Ehc,\r
+  IN  CONST USB2_HC_DEV   *Ehc,\r
   IN  UINT32              Offset\r
   )\r
 {\r
@@ -76,7 +76,7 @@ EhcReadDbgRegister (
                              Ehc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              Ehc->DebugPortBarNum,\r
-                             (UINT64) (Ehc->DebugPortOffset + Offset),\r
+                             Ehc->DebugPortOffset + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -90,6 +90,59 @@ EhcReadDbgRegister (
 }\r
 \r
 \r
+/**\r
+  Check whether the host controller has an in-use debug port.\r
+\r
+  @param[in] Ehc         The Enhanced Host Controller to query.\r
+\r
+  @param[in] PortNumber  If PortNumber is not NULL, then query whether\r
+                         PortNumber is an in-use debug port on Ehc. (PortNumber\r
+                         is taken in UEFI notation, i.e., zero-based.)\r
+                         Otherwise, query whether Ehc has any in-use debug\r
+                         port.\r
+\r
+  @retval TRUE   PortNumber is an in-use debug port on Ehc (if PortNumber is\r
+                 not NULL), or some port on Ehc is an in-use debug port\r
+                 (otherwise).\r
+\r
+  @retval FALSE  PortNumber is not an in-use debug port on Ehc (if PortNumber\r
+                 is not NULL), or no port on Ehc is an in-use debug port\r
+                 (otherwise).\r
+**/\r
+BOOLEAN\r
+EhcIsDebugPortInUse (\r
+  IN CONST USB2_HC_DEV *Ehc,\r
+  IN CONST UINT8       *PortNumber OPTIONAL\r
+  )\r
+{\r
+  UINT32 State;\r
+\r
+  if (Ehc->DebugPortNum == 0) {\r
+    //\r
+    // The host controller has no debug port.\r
+    //\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // The Debug Port Number field in HCSPARAMS is one-based.\r
+  //\r
+  if (PortNumber != NULL && *PortNumber != Ehc->DebugPortNum - 1) {\r
+    //\r
+    // The caller specified a port, but it's not the debug port of the host\r
+    // controller.\r
+    //\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Deduce usage from the Control Register.\r
+  //\r
+  State = EhcReadDbgRegister(Ehc, 0);\r
+  return (State & USB_DEBUG_PORT_IN_USE_MASK) == USB_DEBUG_PORT_IN_USE_MASK;\r
+}\r
+\r
+\r
 /**\r
   Read EHCI Operation register.\r
 \r
@@ -115,7 +168,7 @@ EhcReadOpReg (
                              Ehc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              EHC_BAR_INDEX,\r
-                             (UINT64) (Ehc->CapLen + Offset),\r
+                             Ehc->CapLen + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -152,7 +205,7 @@ EhcWriteOpReg (
                              Ehc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              EHC_BAR_INDEX,\r
-                             (UINT64) (Ehc->CapLen + Offset),\r
+                             Ehc->CapLen + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -372,29 +425,7 @@ EhcEnablePeriodSchd (
 }\r
 \r
 \r
-/**\r
-  Disable periodic schedule.\r
 \r
-  @param  Ehc               The EHCI device.\r
-  @param  Timeout           Time to wait before abort (in millisecond, ms).\r
-\r
-  @retval EFI_SUCCESS       Periodic schedule is disabled.\r
-  @retval EFI_DEVICE_ERROR  Fail to disable periodic schedule.\r
-\r
-**/\r
-EFI_STATUS\r
-EhcDisablePeriodSchd (\r
-  IN USB2_HC_DEV          *Ehc,\r
-  IN UINT32               Timeout\r
-  )\r
-{\r
-  EFI_STATUS              Status;\r
-\r
-  EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);\r
-\r
-  Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_PERIOD_ENABLED, FALSE, Timeout);\r
-  return Status;\r
-}\r
 \r
 \r
 \r
@@ -424,29 +455,7 @@ EhcEnableAsyncSchd (
 \r
 \r
 \r
-/**\r
-  Disable asynchrounous schedule.\r
 \r
-  @param  Ehc          The EHCI device.\r
-  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
-\r
-  @retval EFI_SUCCESS  The asynchronous schedule is disabled.\r
-  @return Others       Failed to disable the asynchronous schedule.\r
-\r
-**/\r
-EFI_STATUS\r
-EhcDisableAsyncSchd (\r
-  IN USB2_HC_DEV          *Ehc,\r
-  IN UINT32               Timeout\r
-  )\r
-{\r
-  EFI_STATUS  Status;\r
-\r
-  EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);\r
-\r
-  Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_ASYNC_ENABLED, FALSE, Timeout);\r
-  return Status;\r
-}\r
 \r
 \r
 \r