\r
The EHCI register operation routines.\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
return Data;\r
}\r
\r
+/**\r
+ Read EHCI debug port register.\r
+\r
+ @param Ehc The EHCI device.\r
+ @param Offset Debug port register offset.\r
+\r
+ @return The register content read.\r
+ @retval If err, return 0xffff.\r
+\r
+**/\r
+UINT32\r
+EhcReadDbgRegister (\r
+ IN CONST USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset\r
+ )\r
+{\r
+ UINT32 Data;\r
+ EFI_STATUS Status;\r
+\r
+ Status = Ehc->PciIo->Mem.Read (\r
+ Ehc->PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Ehc->DebugPortBarNum,\r
+ Ehc->DebugPortOffset + Offset,\r
+ 1,\r
+ &Data\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "EhcReadDbgRegister: Pci Io read error - %r at %d\n", Status, Offset));\r
+ Data = 0xFFFF;\r
+ }\r
+\r
+ return Data;\r
+}\r
+\r
+\r
+/**\r
+ Check whether the host controller has an in-use debug port.\r
+\r
+ @param[in] Ehc The Enhanced Host Controller to query.\r
+\r
+ @param[in] PortNumber If PortNumber is not NULL, then query whether\r
+ PortNumber is an in-use debug port on Ehc. (PortNumber\r
+ is taken in UEFI notation, i.e., zero-based.)\r
+ Otherwise, query whether Ehc has any in-use debug\r
+ port.\r
+\r
+ @retval TRUE PortNumber is an in-use debug port on Ehc (if PortNumber is\r
+ not NULL), or some port on Ehc is an in-use debug port\r
+ (otherwise).\r
+\r
+ @retval FALSE PortNumber is not an in-use debug port on Ehc (if PortNumber\r
+ is not NULL), or no port on Ehc is an in-use debug port\r
+ (otherwise).\r
+**/\r
+BOOLEAN\r
+EhcIsDebugPortInUse (\r
+ IN CONST USB2_HC_DEV *Ehc,\r
+ IN CONST UINT8 *PortNumber OPTIONAL\r
+ )\r
+{\r
+ UINT32 State;\r
+\r
+ if (Ehc->DebugPortNum == 0) {\r
+ //\r
+ // The host controller has no debug port.\r
+ //\r
+ return FALSE;\r
+ }\r
+\r
+ //\r
+ // The Debug Port Number field in HCSPARAMS is one-based.\r
+ //\r
+ if (PortNumber != NULL && *PortNumber != Ehc->DebugPortNum - 1) {\r
+ //\r
+ // The caller specified a port, but it's not the debug port of the host\r
+ // controller.\r
+ //\r
+ return FALSE;\r
+ }\r
+\r
+ //\r
+ // Deduce usage from the Control Register.\r
+ //\r
+ State = EhcReadDbgRegister(Ehc, 0);\r
+ return (State & USB_DEBUG_PORT_IN_USE_MASK) == USB_DEBUG_PORT_IN_USE_MASK;\r
+}\r
+\r
\r
/**\r
Read EHCI Operation register.\r
Ehc->PciIo,\r
EfiPciIoWidthUint32,\r
EHC_BAR_INDEX,\r
- (UINT64) (Ehc->CapLen + Offset),\r
+ Ehc->CapLen + Offset,\r
1,\r
&Data\r
);\r
Ehc->PciIo,\r
EfiPciIoWidthUint32,\r
EHC_BAR_INDEX,\r
- (UINT64) (Ehc->CapLen + Offset),\r
+ Ehc->CapLen + Offset,\r
1,\r
&Data\r
);\r
}\r
\r
\r
-/**\r
- Disable periodic schedule.\r
-\r
- @param Ehc The EHCI device.\r
- @param Timeout Time to wait before abort (in millisecond, ms).\r
-\r
- @retval EFI_SUCCESS Periodic schedule is disabled.\r
- @retval EFI_DEVICE_ERROR Fail to disable periodic schedule.\r
-\r
-**/\r
-EFI_STATUS\r
-EhcDisablePeriodSchd (\r
- IN USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
- )\r
-{\r
- EFI_STATUS Status;\r
-\r
- EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_PERIOD);\r
\r
- Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_PERIOD_ENABLED, FALSE, Timeout);\r
- return Status;\r
-}\r
\r
\r
\r
\r
\r
\r
-/**\r
- Disable asynchrounous schedule.\r
-\r
- @param Ehc The EHCI device.\r
- @param Timeout Time to wait before abort (in millisecond, ms).\r
-\r
- @retval EFI_SUCCESS The asynchronous schedule is disabled.\r
- @return Others Failed to disable the asynchronous schedule.\r
-\r
-**/\r
-EFI_STATUS\r
-EhcDisableAsyncSchd (\r
- IN USB2_HC_DEV *Ehc,\r
- IN UINT32 Timeout\r
- )\r
-{\r
- EFI_STATUS Status;\r
\r
- EhcClearOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_ENABLE_ASYNC);\r
-\r
- Status = EhcWaitOpRegBit (Ehc, EHC_USBSTS_OFFSET, USBSTS_ASYNC_ENABLED, FALSE, Timeout);\r
- return Status;\r
-}\r
\r
\r
\r
)\r
{\r
EFI_STATUS Status;\r
+ UINT32 Index;\r
+ UINT32 RegVal;\r
\r
// This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.\r
// This ASSERT needs to be removed so the BeagleBoard will boot. When we fix\r
// Allocate the periodic frame and associated memeory\r
// management facilities if not already done.\r
//\r
- if (Ehc->PeriodFrameHost != NULL) {\r
+ if (Ehc->PeriodFrame != NULL) {\r
EhcFreeSched (Ehc);\r
}\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
- //\r
- // 1. Program the CTRLDSSEGMENT register with the high 32 bit addr\r
- //\r
- EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, Ehc->High32bitAddr);\r
\r
//\r
- // 2. Clear USBINTR to disable all the interrupt. UEFI works by polling\r
+ // 1. Clear USBINTR to disable all the interrupt. UEFI works by polling\r
//\r
EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);\r
\r
//\r
- // 3. Program periodic frame list, already done in EhcInitSched\r
- // 4. Start the Host Controller\r
+ // 2. Start the Host Controller\r
//\r
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
\r
//\r
- // 5. Set all ports routing to EHC\r
+ // 3. Power up all ports if EHCI has Port Power Control (PPC) support\r
//\r
- EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+ if (Ehc->HcStructParams & HCSP_PPC) {\r
+ for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {\r
+ //\r
+ // Do not clear port status bits on initialization. Otherwise devices will\r
+ // not enumerate properly at startup.\r
+ //\r
+ RegVal = EhcReadOpReg(Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)));\r
+ RegVal &= ~PORTSC_CHANGE_MASK;\r
+ RegVal |= PORTSC_POWER;\r
+ EhcWriteOpReg (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), RegVal);\r
+ }\r
+ }\r
\r
//\r
// Wait roothub port power stable\r
//\r
gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);\r
\r
+ //\r
+ // 4. Set all ports routing to EHC\r
+ //\r
+ EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+\r
Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);\r
\r
if (EFI_ERROR (Status)) {\r
projects / mirror_edk2.git / blobdiff