\r
The EHCI register operation routines.\r
\r
-Copyright (c) 2007 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
return Data;\r
}\r
\r
+/**\r
+ Read EHCI debug port register.\r
+\r
+ @param Ehc The EHCI device.\r
+ @param Offset Debug port register offset.\r
+\r
+ @return The register content read.\r
+ @retval If err, return 0xffff.\r
+\r
+**/\r
+UINT32\r
+EhcReadDbgRegister (\r
+ IN USB2_HC_DEV *Ehc,\r
+ IN UINT32 Offset\r
+ )\r
+{\r
+ UINT32 Data;\r
+ EFI_STATUS Status;\r
+\r
+ Status = Ehc->PciIo->Mem.Read (\r
+ Ehc->PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Ehc->DebugPortBarNum,\r
+ Ehc->DebugPortOffset + Offset,\r
+ 1,\r
+ &Data\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_ERROR, "EhcReadDbgRegister: Pci Io read error - %r at %d\n", Status, Offset));\r
+ Data = 0xFFFF;\r
+ }\r
+\r
+ return Data;\r
+}\r
+\r
\r
/**\r
Read EHCI Operation register.\r
Ehc->PciIo,\r
EfiPciIoWidthUint32,\r
EHC_BAR_INDEX,\r
- (UINT64) (Ehc->CapLen + Offset),\r
+ Ehc->CapLen + Offset,\r
1,\r
&Data\r
);\r
Ehc->PciIo,\r
EfiPciIoWidthUint32,\r
EHC_BAR_INDEX,\r
- (UINT64) (Ehc->CapLen + Offset),\r
+ Ehc->CapLen + Offset,\r
1,\r
&Data\r
);\r
)\r
{\r
EFI_STATUS Status;\r
+ UINT32 Index;\r
+ UINT32 RegVal;\r
\r
// This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.\r
// This ASSERT needs to be removed so the BeagleBoard will boot. When we fix\r
EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);\r
\r
//\r
- // 2. Program periodic frame list, already done in EhcInitSched\r
- // 3. Start the Host Controller\r
+ // 2. Start the Host Controller\r
//\r
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
\r
//\r
- // 4. Set all ports routing to EHC\r
+ // 3. Power up all ports if EHCI has Port Power Control (PPC) support\r
//\r
- EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+ if (Ehc->HcStructParams & HCSP_PPC) {\r
+ for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {\r
+ //\r
+ // Do not clear port status bits on initialization. Otherwise devices will\r
+ // not enumerate properly at startup.\r
+ //\r
+ RegVal = EhcReadOpReg(Ehc, (UINT32)(EHC_PORT_STAT_OFFSET + (4 * Index)));\r
+ RegVal &= ~PORTSC_CHANGE_MASK;\r
+ RegVal |= PORTSC_POWER;\r
+ EhcWriteOpReg (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), RegVal);\r
+ }\r
+ }\r
\r
//\r
// Wait roothub port power stable\r
//\r
gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);\r
\r
+ //\r
+ // 4. Set all ports routing to EHC\r
+ //\r
+ EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+\r
Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);\r
\r
if (EFI_ERROR (Status)) {\r