MdeModulePkg Xhci: Correct description of Timeout param in XhciReg.h

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / UhciQueue.h

diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h
index 70e7f377ded6b699d57147c1bf5ecc9136f49314..9ddca383026dc2f75236c34ce4db986f10668be4 100644 (file)
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciQueue.h
@@ -2,8 +2,8 @@
 \r
   The definition for UHCI register operation routines.\r
 \r
-Copyright (c) 2007, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 http://opensource.org/licenses/bsd-license.php\r
@@ -97,14 +97,14 @@ struct _UHCI_TD_SW {
 /**\r
   Link the TD To QH.\r
 \r
+  @param  Uhc         The UHCI device.\r
   @param  Qh          The queue head for the TD to link to.\r
   @param  Td          The TD to link.\r
 \r
-  @return None.\r
-\r
 **/\r
 VOID\r
 UhciLinkTdToQh (\r
+  IN USB_HC_DEV           *Uhc,\r
   IN UHCI_QH_SW           *Qh,\r
   IN UHCI_TD_SW           *Td\r
   );\r
@@ -212,8 +212,10 @@ UhciCreateQh (
   @param  Uhc         The UHCI device.\r
   @param  DeviceAddr  The device address.\r
   @param  DataPktId   Packet Identification of Data Tds.\r
-  @param  Request     A pointer to request structure buffer to transfer.\r
-  @param  Data        A pointer to user data buffer to transfer.\r
+  @param  Request     A pointer to cpu memory address of request structure buffer to transfer.\r
+  @param  RequestPhy  A pointer to pci memory address of request structure buffer to transfer.\r
+  @param  Data        A pointer to cpu memory address of user data buffer to transfer.\r
+  @param  DataPhy     A pointer to pci memory address of user data buffer to transfer.\r
   @param  DataLen     Length of user data to transfer.\r
   @param  MaxPacket   Maximum packet size for control transfer.\r
   @param  IsLow       Full speed or low speed.\r
@@ -227,7 +229,9 @@ UhciCreateCtrlTds (
   IN UINT8                DeviceAddr,\r
   IN UINT8                DataPktId,\r
   IN UINT8                *Request,\r
+  IN UINT8                *RequestPhy,\r
   IN UINT8                *Data,\r
+  IN UINT8                *DataPhy,\r
   IN UINTN                DataLen,\r
   IN UINT8                MaxPacket,\r
   IN BOOLEAN              IsLow\r
@@ -241,7 +245,8 @@ UhciCreateCtrlTds (
   @param  DevAddr     Address of Device.\r
   @param  EndPoint    Endpoint Number.\r
   @param  PktId       Packet Identification of Data Tds.\r
-  @param  Data        A pointer to user data buffer to transfer.\r
+  @param  Data        A pointer to cpu memory address of user data buffer to transfer.\r
+  @param  DataPhy     A pointer to pci memory address of user data buffer to transfer.\r
   @param  DataLen     Length of user data to transfer.\r
   @param  DataToggle  Data Toggle Pointer.\r
   @param  MaxPacket   Maximum packet size for Bulk/Interrupt transfer.\r
@@ -257,6 +262,7 @@ UhciCreateBulkOrIntTds (
   IN UINT8                EndPoint,\r
   IN UINT8                PktId,\r
   IN UINT8                *Data,\r
+  IN UINT8                *DataPhy,\r
   IN UINTN                DataLen,\r
   IN OUT UINT8            *DataToggle,\r
   IN UINT8                MaxPacket,\r