#ifndef _RECOVERY_UHC_H_\r
#define _RECOVERY_UHC_H_\r
\r
-\r
#include <PiPei.h>\r
\r
#include <Ppi/UsbController.h>\r
#include <Library/IoLib.h>\r
#include <Library/PeiServicesLib.h>\r
\r
-#define USB_SLOW_SPEED_DEVICE 0x01\r
-#define USB_FULL_SPEED_DEVICE 0x02\r
+#define USB_SLOW_SPEED_DEVICE 0x01\r
+#define USB_FULL_SPEED_DEVICE 0x02\r
\r
//\r
// One memory block uses 16 page\r
//\r
-#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16\r
-\r
-#define USBCMD 0 /* Command Register Offset 00-01h */\r
-#define USBCMD_RS BIT0 /* Run/Stop */\r
-#define USBCMD_HCRESET BIT1 /* Host reset */\r
-#define USBCMD_GRESET BIT2 /* Global reset */\r
-#define USBCMD_EGSM BIT3 /* Global Suspend Mode */\r
-#define USBCMD_FGR BIT4 /* Force Global Resume */\r
-#define USBCMD_SWDBG BIT5 /* SW Debug mode */\r
-#define USBCMD_CF BIT6 /* Config Flag (sw only) */\r
-#define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */\r
+#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16\r
+\r
+#define USBCMD 0 /* Command Register Offset 00-01h */\r
+#define USBCMD_RS BIT0 /* Run/Stop */\r
+#define USBCMD_HCRESET BIT1 /* Host reset */\r
+#define USBCMD_GRESET BIT2 /* Global reset */\r
+#define USBCMD_EGSM BIT3 /* Global Suspend Mode */\r
+#define USBCMD_FGR BIT4 /* Force Global Resume */\r
+#define USBCMD_SWDBG BIT5 /* SW Debug mode */\r
+#define USBCMD_CF BIT6 /* Config Flag (sw only) */\r
+#define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */\r
\r
/* Status register */\r
-#define USBSTS 2 /* Status Register Offset 02-03h */\r
-#define USBSTS_USBINT BIT0 /* Interrupt due to IOC */\r
-#define USBSTS_ERROR BIT1 /* Interrupt due to error */\r
-#define USBSTS_RD BIT2 /* Resume Detect */\r
-#define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */\r
-#define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */\r
-#define USBSTS_HCH BIT5 /* HC Halted */\r
+#define USBSTS 2 /* Status Register Offset 02-03h */\r
+#define USBSTS_USBINT BIT0 /* Interrupt due to IOC */\r
+#define USBSTS_ERROR BIT1 /* Interrupt due to error */\r
+#define USBSTS_RD BIT2 /* Resume Detect */\r
+#define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */\r
+#define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */\r
+#define USBSTS_HCH BIT5 /* HC Halted */\r
\r
/* Interrupt enable register */\r
-#define USBINTR 4 /* Interrupt Enable Register 04-05h */\r
-#define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */\r
-#define USBINTR_RESUME BIT1 /* Resume interrupt enable */\r
-#define USBINTR_IOC BIT2 /* Interrupt On Complete enable */\r
-#define USBINTR_SP BIT3 /* Short packet interrupt enable */\r
+#define USBINTR 4 /* Interrupt Enable Register 04-05h */\r
+#define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */\r
+#define USBINTR_RESUME BIT1 /* Resume interrupt enable */\r
+#define USBINTR_IOC BIT2 /* Interrupt On Complete enable */\r
+#define USBINTR_SP BIT3 /* Short packet interrupt enable */\r
\r
/* Frame Number Register Offset 06-08h */\r
#define USBFRNUM 6\r
#define USBSOF 0x0c\r
\r
/* USB port status and control registers */\r
-#define USBPORTSC1 0x10 /*Port 1 offset 10-11h */\r
-#define USBPORTSC2 0x12 /*Port 2 offset 12-13h */\r
-\r
-#define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */\r
-#define USBPORTSC_CSC BIT1 /* Connect Status Change */\r
-#define USBPORTSC_PED BIT2 /* Port Enable / Disable */\r
-#define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */\r
-#define USBPORTSC_LSL BIT4 /* Line Status Low bit*/\r
-#define USBPORTSC_LSH BIT5 /* Line Status High bit*/\r
-#define USBPORTSC_RD BIT6 /* Resume Detect */\r
-#define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */\r
-#define USBPORTSC_PR BIT9 /* Port Reset */\r
-#define USBPORTSC_SUSP BIT12 /* Suspend */\r
-\r
-#define SETUP_PACKET_ID 0x2D\r
-#define INPUT_PACKET_ID 0x69\r
-#define OUTPUT_PACKET_ID 0xE1\r
-#define ERROR_PACKET_ID 0x55\r
+#define USBPORTSC1 0x10 /*Port 1 offset 10-11h */\r
+#define USBPORTSC2 0x12 /*Port 2 offset 12-13h */\r
+\r
+#define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */\r
+#define USBPORTSC_CSC BIT1 /* Connect Status Change */\r
+#define USBPORTSC_PED BIT2 /* Port Enable / Disable */\r
+#define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */\r
+#define USBPORTSC_LSL BIT4 /* Line Status Low bit*/\r
+#define USBPORTSC_LSH BIT5 /* Line Status High bit*/\r
+#define USBPORTSC_RD BIT6 /* Resume Detect */\r
+#define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */\r
+#define USBPORTSC_PR BIT9 /* Port Reset */\r
+#define USBPORTSC_SUSP BIT12 /* Suspend */\r
+\r
+#define SETUP_PACKET_ID 0x2D\r
+#define INPUT_PACKET_ID 0x69\r
+#define OUTPUT_PACKET_ID 0xE1\r
+#define ERROR_PACKET_ID 0x55\r
\r
#define STALL_1_MICRO_SECOND 1\r
#define STALL_1_MILLI_SECOND 1000\r
\r
-\r
#pragma pack(1)\r
\r
typedef struct {\r
- UINT32 FrameListPtrTerminate : 1;\r
- UINT32 FrameListPtrQSelect : 1;\r
- UINT32 FrameListRsvd : 2;\r
- UINT32 FrameListPtr : 28;\r
+ UINT32 FrameListPtrTerminate : 1;\r
+ UINT32 FrameListPtrQSelect : 1;\r
+ UINT32 FrameListRsvd : 2;\r
+ UINT32 FrameListPtr : 28;\r
} FRAMELIST_ENTRY;\r
\r
typedef struct {\r
- UINT32 QHHorizontalTerminate : 1;\r
- UINT32 QHHorizontalQSelect : 1;\r
- UINT32 QHHorizontalRsvd : 2;\r
- UINT32 QHHorizontalPtr : 28;\r
- UINT32 QHVerticalTerminate : 1;\r
- UINT32 QHVerticalQSelect : 1;\r
- UINT32 QHVerticalRsvd : 2;\r
- UINT32 QHVerticalPtr : 28;\r
+ UINT32 QHHorizontalTerminate : 1;\r
+ UINT32 QHHorizontalQSelect : 1;\r
+ UINT32 QHHorizontalRsvd : 2;\r
+ UINT32 QHHorizontalPtr : 28;\r
+ UINT32 QHVerticalTerminate : 1;\r
+ UINT32 QHVerticalQSelect : 1;\r
+ UINT32 QHVerticalRsvd : 2;\r
+ UINT32 QHVerticalPtr : 28;\r
} QUEUE_HEAD;\r
\r
typedef struct {\r
- QUEUE_HEAD QueueHead;\r
- UINT32 Reserved1;\r
- UINT32 Reserved2;\r
- VOID *PtrNext;\r
- VOID *PtrDown;\r
- VOID *Reserved3;\r
- UINT32 Reserved4;\r
+ QUEUE_HEAD QueueHead;\r
+ UINT32 Reserved1;\r
+ UINT32 Reserved2;\r
+ VOID *PtrNext;\r
+ VOID *PtrDown;\r
+ VOID *Reserved3;\r
+ UINT32 Reserved4;\r
} QH_STRUCT;\r
\r
typedef struct {\r
- UINT32 TDLinkPtrTerminate : 1;\r
- UINT32 TDLinkPtrQSelect : 1;\r
- UINT32 TDLinkPtrDepthSelect : 1;\r
- UINT32 TDLinkPtrRsvd : 1;\r
- UINT32 TDLinkPtr : 28;\r
- UINT32 TDStatusActualLength : 11;\r
- UINT32 TDStatusRsvd : 5;\r
- UINT32 TDStatus : 8;\r
- UINT32 TDStatusIOC : 1;\r
- UINT32 TDStatusIOS : 1;\r
- UINT32 TDStatusLS : 1;\r
- UINT32 TDStatusErr : 2;\r
- UINT32 TDStatusSPD : 1;\r
- UINT32 TDStatusRsvd2 : 2;\r
- UINT32 TDTokenPID : 8;\r
- UINT32 TDTokenDevAddr : 7;\r
- UINT32 TDTokenEndPt : 4;\r
- UINT32 TDTokenDataToggle : 1;\r
- UINT32 TDTokenRsvd : 1;\r
- UINT32 TDTokenMaxLen : 11;\r
- UINT32 TDBufferPtr;\r
+ UINT32 TDLinkPtrTerminate : 1;\r
+ UINT32 TDLinkPtrQSelect : 1;\r
+ UINT32 TDLinkPtrDepthSelect : 1;\r
+ UINT32 TDLinkPtrRsvd : 1;\r
+ UINT32 TDLinkPtr : 28;\r
+ UINT32 TDStatusActualLength : 11;\r
+ UINT32 TDStatusRsvd : 5;\r
+ UINT32 TDStatus : 8;\r
+ UINT32 TDStatusIOC : 1;\r
+ UINT32 TDStatusIOS : 1;\r
+ UINT32 TDStatusLS : 1;\r
+ UINT32 TDStatusErr : 2;\r
+ UINT32 TDStatusSPD : 1;\r
+ UINT32 TDStatusRsvd2 : 2;\r
+ UINT32 TDTokenPID : 8;\r
+ UINT32 TDTokenDevAddr : 7;\r
+ UINT32 TDTokenEndPt : 4;\r
+ UINT32 TDTokenDataToggle : 1;\r
+ UINT32 TDTokenRsvd : 1;\r
+ UINT32 TDTokenMaxLen : 11;\r
+ UINT32 TDBufferPtr;\r
} TD;\r
\r
typedef struct {\r
- TD TDData;\r
- UINT8 *PtrTDBuffer;\r
- VOID *PtrNextTD;\r
- VOID *PtrNextQH;\r
- UINT16 TDBufferLength;\r
- UINT16 Reserved;\r
+ TD TDData;\r
+ UINT8 *PtrTDBuffer;\r
+ VOID *PtrNextTD;\r
+ VOID *PtrNextQH;\r
+ UINT16 TDBufferLength;\r
+ UINT16 Reserved;\r
} TD_STRUCT;\r
\r
#pragma pack()\r
typedef struct _MEMORY_MANAGE_HEADER MEMORY_MANAGE_HEADER;\r
\r
struct _MEMORY_MANAGE_HEADER {\r
- UINT8 *BitArrayPtr;\r
- UINTN BitArraySizeInBytes;\r
- UINT8 *MemoryBlockPtr;\r
- UINTN MemoryBlockSizeInBytes;\r
- MEMORY_MANAGE_HEADER *Next;\r
+ UINT8 *BitArrayPtr;\r
+ UINTN BitArraySizeInBytes;\r
+ UINT8 *MemoryBlockPtr;\r
+ UINTN MemoryBlockSizeInBytes;\r
+ MEMORY_MANAGE_HEADER *Next;\r
};\r
\r
-#define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')\r
+#define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')\r
typedef struct {\r
- UINTN Signature;\r
- PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;\r
- EDKII_IOMMU_PPI *IoMmu;\r
- EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r
+ UINTN Signature;\r
+ PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;\r
+ EDKII_IOMMU_PPI *IoMmu;\r
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r
//\r
// EndOfPei callback is used to stop the UHC DMA operation\r
// after exit PEI phase.\r
//\r
- EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
+ EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
\r
- UINT32 UsbHostControllerBaseAddress;\r
- FRAMELIST_ENTRY *FrameListEntry;\r
- QH_STRUCT *ConfigQH;\r
- QH_STRUCT *BulkQH;\r
+ UINT32 UsbHostControllerBaseAddress;\r
+ FRAMELIST_ENTRY *FrameListEntry;\r
+ QH_STRUCT *ConfigQH;\r
+ QH_STRUCT *BulkQH;\r
//\r
// Header1 used for QH,TD memory blocks management\r
//\r
- MEMORY_MANAGE_HEADER *Header1;\r
-\r
+ MEMORY_MANAGE_HEADER *Header1;\r
} USB_UHC_DEV;\r
\r
-#define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)\r
-#define PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY(a) CR (a, USB_UHC_DEV, EndOfPeiNotifyList, USB_UHC_DEV_SIGNATURE)\r
+#define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)\r
+#define PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY(a) CR (a, USB_UHC_DEV, EndOfPeiNotifyList, USB_UHC_DEV_SIGNATURE)\r
\r
/**\r
Submits control transfer to a target USB device.\r
EFI_STATUS\r
EFIAPI\r
UhcControlTransfer (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI * This,\r
- IN UINT8 DeviceAddress,\r
- IN UINT8 DeviceSpeed,\r
- IN UINT8 MaximumPacketLength,\r
- IN EFI_USB_DEVICE_REQUEST * Request,\r
- IN EFI_USB_DATA_DIRECTION TransferDirection,\r
- IN OUT VOID *Data OPTIONAL,\r
- IN OUT UINTN *DataLength OPTIONAL,\r
- IN UINTN TimeOut,\r
- OUT UINT32 *TransferResult\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 DeviceAddress,\r
+ IN UINT8 DeviceSpeed,\r
+ IN UINT8 MaximumPacketLength,\r
+ IN EFI_USB_DEVICE_REQUEST *Request,\r
+ IN EFI_USB_DATA_DIRECTION TransferDirection,\r
+ IN OUT VOID *Data OPTIONAL,\r
+ IN OUT UINTN *DataLength OPTIONAL,\r
+ IN UINTN TimeOut,\r
+ OUT UINT32 *TransferResult\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UhcBulkTransfer (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 DeviceAddress,\r
- IN UINT8 EndPointAddress,\r
- IN UINT8 MaximumPacketLength,\r
- IN OUT VOID *Data,\r
- IN OUT UINTN *DataLength,\r
- IN OUT UINT8 *DataToggle,\r
- IN UINTN TimeOut,\r
- OUT UINT32 *TransferResult\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 DeviceAddress,\r
+ IN UINT8 EndPointAddress,\r
+ IN UINT8 MaximumPacketLength,\r
+ IN OUT VOID *Data,\r
+ IN OUT UINTN *DataLength,\r
+ IN OUT UINT8 *DataToggle,\r
+ IN UINTN TimeOut,\r
+ OUT UINT32 *TransferResult\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UhcGetRootHubPortNumber (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- OUT UINT8 *PortNumber\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ OUT UINT8 *PortNumber\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UhcGetRootHubPortStatus (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 PortNumber,\r
- OUT EFI_USB_PORT_STATUS *PortStatus\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 PortNumber,\r
+ OUT EFI_USB_PORT_STATUS *PortStatus\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UhcSetRootHubPortFeature (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 PortNumber,\r
- IN EFI_USB_PORT_FEATURE PortFeature\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 PortNumber,\r
+ IN EFI_USB_PORT_FEATURE PortFeature\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UhcClearRootHubPortFeature (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
- IN UINT8 PortNumber,\r
- IN EFI_USB_PORT_FEATURE PortFeature\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
+ IN UINT8 PortNumber,\r
+ IN EFI_USB_PORT_FEATURE PortFeature\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
InitializeUsbHC (\r
- IN USB_UHC_DEV *UhcDev\r
+ IN USB_UHC_DEV *UhcDev\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
CreateFrameList (\r
- USB_UHC_DEV *UhcDev\r
+ USB_UHC_DEV *UhcDev\r
);\r
\r
/**\r
**/\r
UINT16\r
USBReadPortW (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 Port\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 Port\r
);\r
\r
/**\r
**/\r
VOID\r
USBWritePortW (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 Port,\r
- IN UINT16 Data\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 Port,\r
+ IN UINT16 Data\r
);\r
\r
/**\r
**/\r
VOID\r
USBWritePortDW (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 Port,\r
- IN UINT32 Data\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 Port,\r
+ IN UINT32 Data\r
);\r
\r
/**\r
**/\r
VOID\r
ClearStatusReg (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 StatusAddr\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 StatusAddr\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsStatusOK (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 StatusRegAddr\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 StatusRegAddr\r
);\r
\r
/**\r
**/\r
VOID\r
SetFrameListBaseAddress (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 FrameListRegAddr,\r
- IN UINT32 Addr\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 FrameListRegAddr,\r
+ IN UINT32 Addr\r
);\r
\r
/**\r
IN BOOLEAN IsValid\r
);\r
\r
-\r
/**\r
Allocate TD or QH Struct.\r
\r
**/\r
EFI_STATUS\r
AllocateTDorQHStruct (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT32 Size,\r
- OUT VOID **PtrStruct\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT32 Size,\r
+ OUT VOID **PtrStruct\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
CreateTD (\r
- IN USB_UHC_DEV *UhcDev,\r
- OUT TD_STRUCT **PtrTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ OUT TD_STRUCT **PtrTD\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
GenSetupStageTD (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT8 DevAddr,\r
- IN UINT8 Endpoint,\r
- IN UINT8 DeviceSpeed,\r
- IN UINT8 *DevRequest,\r
- IN UINT8 *RequestPhy,\r
- IN UINT8 RequestLen,\r
- OUT TD_STRUCT **PtrTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT8 DevAddr,\r
+ IN UINT8 Endpoint,\r
+ IN UINT8 DeviceSpeed,\r
+ IN UINT8 *DevRequest,\r
+ IN UINT8 *RequestPhy,\r
+ IN UINT8 RequestLen,\r
+ OUT TD_STRUCT **PtrTD\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
GenDataTD (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT8 DevAddr,\r
- IN UINT8 Endpoint,\r
- IN UINT8 *PtrData,\r
- IN UINT8 *DataPhy,\r
- IN UINT8 Len,\r
- IN UINT8 PktID,\r
- IN UINT8 Toggle,\r
- IN UINT8 DeviceSpeed,\r
- OUT TD_STRUCT **PtrTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT8 DevAddr,\r
+ IN UINT8 Endpoint,\r
+ IN UINT8 *PtrData,\r
+ IN UINT8 *DataPhy,\r
+ IN UINT8 Len,\r
+ IN UINT8 PktID,\r
+ IN UINT8 Toggle,\r
+ IN UINT8 DeviceSpeed,\r
+ OUT TD_STRUCT **PtrTD\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
CreateStatusTD (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT8 DevAddr,\r
- IN UINT8 Endpoint,\r
- IN UINT8 PktID,\r
- IN UINT8 DeviceSpeed,\r
- OUT TD_STRUCT **PtrTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT8 DevAddr,\r
+ IN UINT8 Endpoint,\r
+ IN UINT8 PktID,\r
+ IN UINT8 DeviceSpeed,\r
+ OUT TD_STRUCT **PtrTD\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDLinkPtrValidorInvalid (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsValid\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsValid\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDLinkPtrQHorTDSelect (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsQH\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsQH\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDLinkPtrDepthorBreadth (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsDepth\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsDepth\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDLinkPtr (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN VOID *PtrNext\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN VOID *PtrNext\r
);\r
\r
/**\r
@retval Get TD Link Pointer in TD.\r
\r
**/\r
-VOID*\r
+VOID *\r
GetTDLinkPtr (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
-\r
/**\r
Enable/Disable short packet detection mechanism.\r
\r
**/\r
VOID\r
EnableorDisableTDShortPacket (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsEnable\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsEnable\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDControlErrorCounter (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINT8 MaxErrors\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINT8 MaxErrors\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDLoworFullSpeedDevice (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsLowSpeedDevice\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsLowSpeedDevice\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDControlIsochronousorNot (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsIsochronous\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsIsochronous\r
);\r
\r
/**\r
**/\r
VOID\r
SetorClearTDControlIOC (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsSet\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsSet\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDStatusActiveorInactive (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN BOOLEAN IsActive\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN BOOLEAN IsActive\r
);\r
\r
/**\r
**/\r
UINT16\r
SetTDTokenMaxLength (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINT16 MaxLen\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINT16 MaxLen\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDTokenDataToggle1 (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDTokenDataToggle0 (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDTokenEndPoint (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINTN EndPoint\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINTN EndPoint\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDTokenDeviceAddress (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINTN DevAddr\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINTN DevAddr\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDTokenPacketID (\r
- IN TD_STRUCT *PtrTDStruct,\r
- IN UINT8 PacketID\r
+ IN TD_STRUCT *PtrTDStruct,\r
+ IN UINT8 PacketID\r
);\r
\r
/**\r
**/\r
VOID\r
SetTDDataBuffer (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusActive (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusStalled (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusBufferError (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusBabbleError (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusNAKReceived (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusCRCTimeOutError (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsTDStatusBitStuffError (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
UINT16\r
GetTDStatusActualLength (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
GetTDLinkPtrValidorInvalid (\r
- IN TD_STRUCT *PtrTDStruct\r
+ IN TD_STRUCT *PtrTDStruct\r
);\r
\r
/**\r
**/\r
UINTN\r
CountTDsNumber (\r
- IN TD_STRUCT *PtrFirstTD\r
+ IN TD_STRUCT *PtrFirstTD\r
);\r
\r
/**\r
**/\r
VOID\r
LinkTDToQH (\r
- IN QH_STRUCT *PtrQH,\r
- IN TD_STRUCT *PtrTD\r
+ IN QH_STRUCT *PtrQH,\r
+ IN TD_STRUCT *PtrTD\r
);\r
\r
/**\r
**/\r
VOID\r
LinkTDToTD (\r
- IN TD_STRUCT *PtrPreTD,\r
- IN TD_STRUCT *PtrTD\r
+ IN TD_STRUCT *PtrPreTD,\r
+ IN TD_STRUCT *PtrTD\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExecuteControlTransfer (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN TD_STRUCT *PtrTD,\r
- OUT UINTN *ActualLen,\r
- IN UINTN TimeOut,\r
- OUT UINT32 *TransferResult\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN TD_STRUCT *PtrTD,\r
+ OUT UINTN *ActualLen,\r
+ IN UINTN TimeOut,\r
+ OUT UINT32 *TransferResult\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExecBulkTransfer (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN TD_STRUCT *PtrTD,\r
- IN OUT UINTN *ActualLen,\r
- IN UINT8 *DataToggle,\r
- IN UINTN TimeOut,\r
- OUT UINT32 *TransferResult\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN TD_STRUCT *PtrTD,\r
+ IN OUT UINTN *ActualLen,\r
+ IN UINT8 *DataToggle,\r
+ IN UINTN TimeOut,\r
+ OUT UINT32 *TransferResult\r
);\r
\r
/**\r
**/\r
VOID\r
DeleteQueuedTDs (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN TD_STRUCT *PtrFirstTD\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN TD_STRUCT *PtrFirstTD\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
CheckTDsResults (\r
- IN TD_STRUCT *PtrTD,\r
- OUT UINT32 *Result,\r
- OUT UINTN *ErrTDPos,\r
- OUT UINTN *ActualTransferSize\r
+ IN TD_STRUCT *PtrTD,\r
+ OUT UINT32 *Result,\r
+ OUT UINTN *ErrTDPos,\r
+ OUT UINTN *ActualTransferSize\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
InitializeMemoryManagement (\r
- IN USB_UHC_DEV *UhcDev\r
+ IN USB_UHC_DEV *UhcDev\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
UhcAllocatePool (\r
- IN USB_UHC_DEV *UhcDev,\r
- OUT UINT8 **Pool,\r
- IN UINTN AllocSize\r
+ IN USB_UHC_DEV *UhcDev,\r
+ OUT UINT8 **Pool,\r
+ IN UINTN AllocSize\r
);\r
\r
/**\r
**/\r
VOID\r
UhcFreePool (\r
- IN USB_UHC_DEV *UhcDev,\r
- IN UINT8 *Pool,\r
- IN UINTN AllocSize\r
+ IN USB_UHC_DEV *UhcDev,\r
+ IN UINT8 *Pool,\r
+ IN UINTN AllocSize\r
);\r
\r
/**\r
IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
);\r
\r
-\r
/**\r
Map address of request structure buffer.\r
\r
**/\r
EFI_STATUS\r
UhciMapUserRequest (\r
- IN USB_UHC_DEV *Uhc,\r
- IN OUT VOID *Request,\r
- OUT UINT8 **MappedAddr,\r
- OUT VOID **Map\r
+ IN USB_UHC_DEV *Uhc,\r
+ IN OUT VOID *Request,\r
+ OUT UINT8 **MappedAddr,\r
+ OUT VOID **Map\r
);\r
\r
/**\r
**/\r
VOID\r
IoMmuUnmap (\r
- IN EDKII_IOMMU_PPI *IoMmu,\r
- IN VOID *Mapping\r
+ IN EDKII_IOMMU_PPI *IoMmu,\r
+ IN VOID *Mapping\r
);\r
\r
/**\r
OUT VOID **Mapping\r
);\r
\r
-\r
/**\r
Initialize IOMMU.\r
\r
**/\r
VOID\r
IoMmuInit (\r
- OUT EDKII_IOMMU_PPI **IoMmu\r
+ OUT EDKII_IOMMU_PPI **IoMmu\r
);\r
\r
#endif\r
projects / mirror_edk2.git / blobdiff