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1 /** @file
2 Private Header file for Usb Host Controller PEIM
3
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #ifndef _RECOVERY_UHC_H_
11 #define _RECOVERY_UHC_H_
12
13
14 #include <PiPei.h>
15
16 #include <Ppi/UsbController.h>
17 #include <Ppi/UsbHostController.h>
18 #include <Ppi/IoMmu.h>
19 #include <Ppi/EndOfPeiPhase.h>
20
21 #include <Library/DebugLib.h>
22 #include <Library/PeimEntryPoint.h>
23 #include <Library/PeiServicesLib.h>
24 #include <Library/BaseMemoryLib.h>
25 #include <Library/TimerLib.h>
26 #include <Library/IoLib.h>
27 #include <Library/PeiServicesLib.h>
28
29 #define USB_SLOW_SPEED_DEVICE 0x01
30 #define USB_FULL_SPEED_DEVICE 0x02
31
32 //
33 // One memory block uses 16 page
34 //
35 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16
36
37 #define USBCMD 0 /* Command Register Offset 00-01h */
38 #define USBCMD_RS BIT0 /* Run/Stop */
39 #define USBCMD_HCRESET BIT1 /* Host reset */
40 #define USBCMD_GRESET BIT2 /* Global reset */
41 #define USBCMD_EGSM BIT3 /* Global Suspend Mode */
42 #define USBCMD_FGR BIT4 /* Force Global Resume */
43 #define USBCMD_SWDBG BIT5 /* SW Debug mode */
44 #define USBCMD_CF BIT6 /* Config Flag (sw only) */
45 #define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */
46
47 /* Status register */
48 #define USBSTS 2 /* Status Register Offset 02-03h */
49 #define USBSTS_USBINT BIT0 /* Interrupt due to IOC */
50 #define USBSTS_ERROR BIT1 /* Interrupt due to error */
51 #define USBSTS_RD BIT2 /* Resume Detect */
52 #define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */
53 #define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */
54 #define USBSTS_HCH BIT5 /* HC Halted */
55
56 /* Interrupt enable register */
57 #define USBINTR 4 /* Interrupt Enable Register 04-05h */
58 #define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */
59 #define USBINTR_RESUME BIT1 /* Resume interrupt enable */
60 #define USBINTR_IOC BIT2 /* Interrupt On Complete enable */
61 #define USBINTR_SP BIT3 /* Short packet interrupt enable */
62
63 /* Frame Number Register Offset 06-08h */
64 #define USBFRNUM 6
65
66 /* Frame List Base Address Register Offset 08-0Bh */
67 #define USBFLBASEADD 8
68
69 /* Start of Frame Modify Register Offset 0Ch */
70 #define USBSOF 0x0c
71
72 /* USB port status and control registers */
73 #define USBPORTSC1 0x10 /*Port 1 offset 10-11h */
74 #define USBPORTSC2 0x12 /*Port 2 offset 12-13h */
75
76 #define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */
77 #define USBPORTSC_CSC BIT1 /* Connect Status Change */
78 #define USBPORTSC_PED BIT2 /* Port Enable / Disable */
79 #define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */
80 #define USBPORTSC_LSL BIT4 /* Line Status Low bit*/
81 #define USBPORTSC_LSH BIT5 /* Line Status High bit*/
82 #define USBPORTSC_RD BIT6 /* Resume Detect */
83 #define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */
84 #define USBPORTSC_PR BIT9 /* Port Reset */
85 #define USBPORTSC_SUSP BIT12 /* Suspend */
86
87 #define SETUP_PACKET_ID 0x2D
88 #define INPUT_PACKET_ID 0x69
89 #define OUTPUT_PACKET_ID 0xE1
90 #define ERROR_PACKET_ID 0x55
91
92 #define STALL_1_MICRO_SECOND 1
93 #define STALL_1_MILLI_SECOND 1000
94
95
96 #pragma pack(1)
97
98 typedef struct {
99 UINT32 FrameListPtrTerminate : 1;
100 UINT32 FrameListPtrQSelect : 1;
101 UINT32 FrameListRsvd : 2;
102 UINT32 FrameListPtr : 28;
103 } FRAMELIST_ENTRY;
104
105 typedef struct {
106 UINT32 QHHorizontalTerminate : 1;
107 UINT32 QHHorizontalQSelect : 1;
108 UINT32 QHHorizontalRsvd : 2;
109 UINT32 QHHorizontalPtr : 28;
110 UINT32 QHVerticalTerminate : 1;
111 UINT32 QHVerticalQSelect : 1;
112 UINT32 QHVerticalRsvd : 2;
113 UINT32 QHVerticalPtr : 28;
114 } QUEUE_HEAD;
115
116 typedef struct {
117 QUEUE_HEAD QueueHead;
118 UINT32 Reserved1;
119 UINT32 Reserved2;
120 VOID *PtrNext;
121 VOID *PtrDown;
122 VOID *Reserved3;
123 UINT32 Reserved4;
124 } QH_STRUCT;
125
126 typedef struct {
127 UINT32 TDLinkPtrTerminate : 1;
128 UINT32 TDLinkPtrQSelect : 1;
129 UINT32 TDLinkPtrDepthSelect : 1;
130 UINT32 TDLinkPtrRsvd : 1;
131 UINT32 TDLinkPtr : 28;
132 UINT32 TDStatusActualLength : 11;
133 UINT32 TDStatusRsvd : 5;
134 UINT32 TDStatus : 8;
135 UINT32 TDStatusIOC : 1;
136 UINT32 TDStatusIOS : 1;
137 UINT32 TDStatusLS : 1;
138 UINT32 TDStatusErr : 2;
139 UINT32 TDStatusSPD : 1;
140 UINT32 TDStatusRsvd2 : 2;
141 UINT32 TDTokenPID : 8;
142 UINT32 TDTokenDevAddr : 7;
143 UINT32 TDTokenEndPt : 4;
144 UINT32 TDTokenDataToggle : 1;
145 UINT32 TDTokenRsvd : 1;
146 UINT32 TDTokenMaxLen : 11;
147 UINT32 TDBufferPtr;
148 } TD;
149
150 typedef struct {
151 TD TDData;
152 UINT8 *PtrTDBuffer;
153 VOID *PtrNextTD;
154 VOID *PtrNextQH;
155 UINT16 TDBufferLength;
156 UINT16 Reserved;
157 } TD_STRUCT;
158
159 #pragma pack()
160
161 typedef struct _MEMORY_MANAGE_HEADER MEMORY_MANAGE_HEADER;
162
163 struct _MEMORY_MANAGE_HEADER {
164 UINT8 *BitArrayPtr;
165 UINTN BitArraySizeInBytes;
166 UINT8 *MemoryBlockPtr;
167 UINTN MemoryBlockSizeInBytes;
168 MEMORY_MANAGE_HEADER *Next;
169 };
170
171 #define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')
172 typedef struct {
173 UINTN Signature;
174 PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;
175 EDKII_IOMMU_PPI *IoMmu;
176 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
177 //
178 // EndOfPei callback is used to stop the UHC DMA operation
179 // after exit PEI phase.
180 //
181 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
182
183 UINT32 UsbHostControllerBaseAddress;
184 FRAMELIST_ENTRY *FrameListEntry;
185 QH_STRUCT *ConfigQH;
186 QH_STRUCT *BulkQH;
187 //
188 // Header1 used for QH,TD memory blocks management
189 //
190 MEMORY_MANAGE_HEADER *Header1;
191
192 } USB_UHC_DEV;
193
194 #define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)
195 #define PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY(a) CR (a, USB_UHC_DEV, EndOfPeiNotifyList, USB_UHC_DEV_SIGNATURE)
196
197 /**
198 Submits control transfer to a target USB device.
199
200 @param PeiServices The pointer of EFI_PEI_SERVICES.
201 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
202 @param DeviceAddress The target device address.
203 @param DeviceSpeed Target device speed.
204 @param MaximumPacketLength Maximum packet size the default control transfer
205 endpoint is capable of sending or receiving.
206 @param Request USB device request to send.
207 @param TransferDirection Specifies the data direction for the data stage.
208 @param Data Data buffer to be transmitted or received from USB device.
209 @param DataLength The size (in bytes) of the data buffer.
210 @param TimeOut Indicates the maximum timeout, in millisecond.
211 @param TransferResult Return the result of this control transfer.
212
213 @retval EFI_SUCCESS Transfer was completed successfully.
214 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resources.
215 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
216 @retval EFI_TIMEOUT Transfer failed due to timeout.
217 @retval EFI_DEVICE_ERROR Transfer failed due to host controller or device error.
218
219 **/
220 EFI_STATUS
221 EFIAPI
222 UhcControlTransfer (
223 IN EFI_PEI_SERVICES **PeiServices,
224 IN PEI_USB_HOST_CONTROLLER_PPI * This,
225 IN UINT8 DeviceAddress,
226 IN UINT8 DeviceSpeed,
227 IN UINT8 MaximumPacketLength,
228 IN EFI_USB_DEVICE_REQUEST * Request,
229 IN EFI_USB_DATA_DIRECTION TransferDirection,
230 IN OUT VOID *Data OPTIONAL,
231 IN OUT UINTN *DataLength OPTIONAL,
232 IN UINTN TimeOut,
233 OUT UINT32 *TransferResult
234 );
235
236 /**
237 Submits bulk transfer to a bulk endpoint of a USB device.
238
239 @param PeiServices The pointer of EFI_PEI_SERVICES.
240 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
241 @param DeviceAddress Target device address.
242 @param EndPointAddress Endpoint number and its direction in bit 7.
243 @param MaximumPacketLength Maximum packet size the endpoint is capable of
244 sending or receiving.
245 @param Data Array of pointers to the buffers of data to transmit
246 from or receive into.
247 @param DataLength The lenght of the data buffer.
248 @param DataToggle On input, the initial data toggle for the transfer;
249 On output, it is updated to to next data toggle to use of
250 the subsequent bulk transfer.
251 @param TimeOut Indicates the maximum time, in millisecond, which the
252 transfer is allowed to complete.
253 @param TransferResult A pointer to the detailed result information of the
254 bulk transfer.
255
256 @retval EFI_SUCCESS The transfer was completed successfully.
257 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
258 @retval EFI_INVALID_PARAMETER Parameters are invalid.
259 @retval EFI_TIMEOUT The transfer failed due to timeout.
260 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
261
262 **/
263 EFI_STATUS
264 EFIAPI
265 UhcBulkTransfer (
266 IN EFI_PEI_SERVICES **PeiServices,
267 IN PEI_USB_HOST_CONTROLLER_PPI *This,
268 IN UINT8 DeviceAddress,
269 IN UINT8 EndPointAddress,
270 IN UINT8 MaximumPacketLength,
271 IN OUT VOID *Data,
272 IN OUT UINTN *DataLength,
273 IN OUT UINT8 *DataToggle,
274 IN UINTN TimeOut,
275 OUT UINT32 *TransferResult
276 );
277
278 /**
279 Retrieves the number of root hub ports.
280
281 @param[in] PeiServices The pointer to the PEI Services Table.
282 @param[in] This The pointer to this instance of the
283 PEI_USB_HOST_CONTROLLER_PPI.
284 @param[out] PortNumber The pointer to the number of the root hub ports.
285
286 @retval EFI_SUCCESS The port number was retrieved successfully.
287 @retval EFI_INVALID_PARAMETER PortNumber is NULL.
288
289 **/
290 EFI_STATUS
291 EFIAPI
292 UhcGetRootHubPortNumber (
293 IN EFI_PEI_SERVICES **PeiServices,
294 IN PEI_USB_HOST_CONTROLLER_PPI *This,
295 OUT UINT8 *PortNumber
296 );
297
298 /**
299 Retrieves the current status of a USB root hub port.
300
301 @param PeiServices The pointer of EFI_PEI_SERVICES.
302 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
303 @param PortNumber The root hub port to retrieve the state from.
304 @param PortStatus Variable to receive the port state.
305
306 @retval EFI_SUCCESS The status of the USB root hub port specified.
307 by PortNumber was returned in PortStatus.
308 @retval EFI_INVALID_PARAMETER PortNumber is invalid.
309
310 **/
311 EFI_STATUS
312 EFIAPI
313 UhcGetRootHubPortStatus (
314 IN EFI_PEI_SERVICES **PeiServices,
315 IN PEI_USB_HOST_CONTROLLER_PPI *This,
316 IN UINT8 PortNumber,
317 OUT EFI_USB_PORT_STATUS *PortStatus
318 );
319
320 /**
321 Sets a feature for the specified root hub port.
322
323 @param PeiServices The pointer of EFI_PEI_SERVICES
324 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI
325 @param PortNumber Root hub port to set.
326 @param PortFeature Feature to set.
327
328 @retval EFI_SUCCESS The feature specified by PortFeature was set.
329 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
330 @retval EFI_TIMEOUT The time out occurred.
331
332 **/
333 EFI_STATUS
334 EFIAPI
335 UhcSetRootHubPortFeature (
336 IN EFI_PEI_SERVICES **PeiServices,
337 IN PEI_USB_HOST_CONTROLLER_PPI *This,
338 IN UINT8 PortNumber,
339 IN EFI_USB_PORT_FEATURE PortFeature
340 );
341
342 /**
343 Clears a feature for the specified root hub port.
344
345 @param PeiServices The pointer of EFI_PEI_SERVICES.
346 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
347 @param PortNumber Specifies the root hub port whose feature
348 is requested to be cleared.
349 @param PortFeature Indicates the feature selector associated with the
350 feature clear request.
351
352 @retval EFI_SUCCESS The feature specified by PortFeature was cleared
353 for the USB root hub port specified by PortNumber.
354 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
355
356 **/
357 EFI_STATUS
358 EFIAPI
359 UhcClearRootHubPortFeature (
360 IN EFI_PEI_SERVICES **PeiServices,
361 IN PEI_USB_HOST_CONTROLLER_PPI *This,
362 IN UINT8 PortNumber,
363 IN EFI_USB_PORT_FEATURE PortFeature
364 );
365
366 /**
367 Initialize UHCI.
368
369 @param UhcDev UHCI Device.
370
371 @retval EFI_SUCCESS UHCI successfully initialized.
372 @retval EFI_OUT_OF_RESOURCES Resource can not be allocated.
373
374 **/
375 EFI_STATUS
376 InitializeUsbHC (
377 IN USB_UHC_DEV *UhcDev
378 );
379
380 /**
381 Create Frame List Structure.
382
383 @param UhcDev UHCI device.
384
385 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
386 @retval EFI_SUCCESS Success.
387
388 **/
389 EFI_STATUS
390 CreateFrameList (
391 USB_UHC_DEV *UhcDev
392 );
393
394 /**
395 Read a 16bit width data from Uhc HC IO space register.
396
397 @param UhcDev The UHCI device.
398 @param Port The IO space address of the register.
399
400 @retval the register content read.
401
402 **/
403 UINT16
404 USBReadPortW (
405 IN USB_UHC_DEV *UhcDev,
406 IN UINT32 Port
407 );
408
409 /**
410 Write a 16bit width data into Uhc HC IO space register.
411
412 @param UhcDev The UHCI device.
413 @param Port The IO space address of the register.
414 @param Data The data written into the register.
415
416 **/
417 VOID
418 USBWritePortW (
419 IN USB_UHC_DEV *UhcDev,
420 IN UINT32 Port,
421 IN UINT16 Data
422 );
423
424 /**
425 Write a 32bit width data into Uhc HC IO space register.
426
427 @param UhcDev The UHCI device.
428 @param Port The IO space address of the register.
429 @param Data The data written into the register.
430
431 **/
432 VOID
433 USBWritePortDW (
434 IN USB_UHC_DEV *UhcDev,
435 IN UINT32 Port,
436 IN UINT32 Data
437 );
438
439 /**
440 Clear the content of UHCI's Status Register.
441
442 @param UhcDev The UHCI device.
443 @param StatusAddr The IO space address of the register.
444
445 **/
446 VOID
447 ClearStatusReg (
448 IN USB_UHC_DEV *UhcDev,
449 IN UINT32 StatusAddr
450 );
451
452 /**
453 Check whether the host controller operates well.
454
455 @param UhcDev The UHCI device.
456 @param StatusRegAddr The io address of status register.
457
458 @retval TRUE Host controller is working.
459 @retval FALSE Host controller is halted or system error.
460
461 **/
462 BOOLEAN
463 IsStatusOK (
464 IN USB_UHC_DEV *UhcDev,
465 IN UINT32 StatusRegAddr
466 );
467
468 /**
469 Set Frame List Base Address.
470
471 @param UhcDev The UHCI device.
472 @param FrameListRegAddr The address of frame list register.
473 @param Addr The address of frame list table.
474
475 **/
476 VOID
477 SetFrameListBaseAddress (
478 IN USB_UHC_DEV *UhcDev,
479 IN UINT32 FrameListRegAddr,
480 IN UINT32 Addr
481 );
482
483 /**
484 Create QH and initialize.
485
486 @param UhcDev The UHCI device.
487 @param PtrQH Place to store QH_STRUCT pointer.
488
489 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
490 @retval EFI_SUCCESS Success.
491
492 **/
493 EFI_STATUS
494 CreateQH (
495 IN USB_UHC_DEV *UhcDev,
496 OUT QH_STRUCT **PtrQH
497 );
498
499 /**
500 Set the horizontal link pointer in QH.
501
502 @param PtrQH Place to store QH_STRUCT pointer.
503 @param PtrNext Place to the next QH_STRUCT.
504
505 **/
506 VOID
507 SetQHHorizontalLinkPtr (
508 IN QH_STRUCT *PtrQH,
509 IN VOID *PtrNext
510 );
511
512 /**
513 Set a QH or TD horizontally to be connected with a specific QH.
514
515 @param PtrQH Place to store QH_STRUCT pointer.
516 @param IsQH Specify QH or TD is connected.
517
518 **/
519 VOID
520 SetQHHorizontalQHorTDSelect (
521 IN QH_STRUCT *PtrQH,
522 IN BOOLEAN IsQH
523 );
524
525 /**
526 Set the horizontal validor bit in QH.
527
528 @param PtrQH Place to store QH_STRUCT pointer.
529 @param IsValid Specify the horizontal linker is valid or not.
530
531 **/
532 VOID
533 SetQHHorizontalValidorInvalid (
534 IN QH_STRUCT *PtrQH,
535 IN BOOLEAN IsValid
536 );
537
538 /**
539 Set the vertical link pointer in QH.
540
541 @param PtrQH Place to store QH_STRUCT pointer.
542 @param PtrNext Place to the next QH_STRUCT.
543
544 **/
545 VOID
546 SetQHVerticalLinkPtr (
547 IN QH_STRUCT *PtrQH,
548 IN VOID *PtrNext
549 );
550
551 /**
552 Set a QH or TD vertically to be connected with a specific QH.
553
554 @param PtrQH Place to store QH_STRUCT pointer.
555 @param IsQH Specify QH or TD is connected.
556
557 **/
558 VOID
559 SetQHVerticalQHorTDSelect (
560 IN QH_STRUCT *PtrQH,
561 IN BOOLEAN IsQH
562 );
563
564 /**
565 Set the vertical validor bit in QH.
566
567 @param PtrQH Place to store QH_STRUCT pointer.
568 @param IsValid Specify the vertical linker is valid or not.
569
570 **/
571 VOID
572 SetQHVerticalValidorInvalid (
573 IN QH_STRUCT *PtrQH,
574 IN BOOLEAN IsValid
575 );
576
577
578 /**
579 Allocate TD or QH Struct.
580
581 @param UhcDev The UHCI device.
582 @param Size The size of allocation.
583 @param PtrStruct Place to store TD_STRUCT pointer.
584
585 @return EFI_SUCCESS Allocate successfully.
586 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
587
588 **/
589 EFI_STATUS
590 AllocateTDorQHStruct (
591 IN USB_UHC_DEV *UhcDev,
592 IN UINT32 Size,
593 OUT VOID **PtrStruct
594 );
595
596 /**
597 Create a TD Struct.
598
599 @param UhcDev The UHCI device.
600 @param PtrTD Place to store TD_STRUCT pointer.
601
602 @return EFI_SUCCESS Allocate successfully.
603 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
604
605 **/
606 EFI_STATUS
607 CreateTD (
608 IN USB_UHC_DEV *UhcDev,
609 OUT TD_STRUCT **PtrTD
610 );
611
612 /**
613 Generate Setup Stage TD.
614
615 @param UhcDev The UHCI device.
616 @param DevAddr Device address.
617 @param Endpoint Endpoint number.
618 @param DeviceSpeed Device Speed.
619 @param DevRequest CPU memory address of request structure buffer to transfer.
620 @param RequestPhy PCI memory address of request structure buffer to transfer.
621 @param RequestLen Request length.
622 @param PtrTD TD_STRUCT generated.
623
624 @return EFI_SUCCESS Generate setup stage TD successfully.
625 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
626
627 **/
628 EFI_STATUS
629 GenSetupStageTD (
630 IN USB_UHC_DEV *UhcDev,
631 IN UINT8 DevAddr,
632 IN UINT8 Endpoint,
633 IN UINT8 DeviceSpeed,
634 IN UINT8 *DevRequest,
635 IN UINT8 *RequestPhy,
636 IN UINT8 RequestLen,
637 OUT TD_STRUCT **PtrTD
638 );
639
640 /**
641 Generate Data Stage TD.
642
643 @param UhcDev The UHCI device.
644 @param DevAddr Device address.
645 @param Endpoint Endpoint number.
646 @param PtrData CPU memory address of user data buffer to transfer.
647 @param DataPhy PCI memory address of user data buffer to transfer.
648 @param Len Data length.
649 @param PktID PacketID.
650 @param Toggle Data toggle value.
651 @param DeviceSpeed Device Speed.
652 @param PtrTD TD_STRUCT generated.
653
654 @return EFI_SUCCESS Generate data stage TD successfully.
655 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
656
657 **/
658 EFI_STATUS
659 GenDataTD (
660 IN USB_UHC_DEV *UhcDev,
661 IN UINT8 DevAddr,
662 IN UINT8 Endpoint,
663 IN UINT8 *PtrData,
664 IN UINT8 *DataPhy,
665 IN UINT8 Len,
666 IN UINT8 PktID,
667 IN UINT8 Toggle,
668 IN UINT8 DeviceSpeed,
669 OUT TD_STRUCT **PtrTD
670 );
671
672 /**
673 Generate Status Stage TD.
674
675 @param UhcDev The UHCI device.
676 @param DevAddr Device address.
677 @param Endpoint Endpoint number.
678 @param PktID PacketID.
679 @param DeviceSpeed Device Speed.
680 @param PtrTD TD_STRUCT generated.
681
682 @return EFI_SUCCESS Generate status stage TD successfully.
683 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
684
685 **/
686 EFI_STATUS
687 CreateStatusTD (
688 IN USB_UHC_DEV *UhcDev,
689 IN UINT8 DevAddr,
690 IN UINT8 Endpoint,
691 IN UINT8 PktID,
692 IN UINT8 DeviceSpeed,
693 OUT TD_STRUCT **PtrTD
694 );
695
696 /**
697 Set the link pointer validor bit in TD.
698
699 @param PtrTDStruct Place to store TD_STRUCT pointer.
700 @param IsValid Specify the linker pointer is valid or not.
701
702 **/
703 VOID
704 SetTDLinkPtrValidorInvalid (
705 IN TD_STRUCT *PtrTDStruct,
706 IN BOOLEAN IsValid
707 );
708
709 /**
710 Set the Link Pointer pointing to a QH or TD.
711
712 @param PtrTDStruct Place to store TD_STRUCT pointer.
713 @param IsQH Specify QH or TD is connected.
714
715 **/
716 VOID
717 SetTDLinkPtrQHorTDSelect (
718 IN TD_STRUCT *PtrTDStruct,
719 IN BOOLEAN IsQH
720 );
721
722 /**
723 Set the traverse is depth-first or breadth-first.
724
725 @param PtrTDStruct Place to store TD_STRUCT pointer.
726 @param IsDepth Specify the traverse is depth-first or breadth-first.
727
728 **/
729 VOID
730 SetTDLinkPtrDepthorBreadth (
731 IN TD_STRUCT *PtrTDStruct,
732 IN BOOLEAN IsDepth
733 );
734
735 /**
736 Set TD Link Pointer in TD.
737
738 @param PtrTDStruct Place to store TD_STRUCT pointer.
739 @param PtrNext Place to the next TD_STRUCT.
740
741 **/
742 VOID
743 SetTDLinkPtr (
744 IN TD_STRUCT *PtrTDStruct,
745 IN VOID *PtrNext
746 );
747
748 /**
749 Get TD Link Pointer.
750
751 @param PtrTDStruct Place to store TD_STRUCT pointer.
752
753 @retval Get TD Link Pointer in TD.
754
755 **/
756 VOID*
757 GetTDLinkPtr (
758 IN TD_STRUCT *PtrTDStruct
759 );
760
761
762 /**
763 Enable/Disable short packet detection mechanism.
764
765 @param PtrTDStruct Place to store TD_STRUCT pointer.
766 @param IsEnable Enable or disable short packet detection mechanism.
767
768 **/
769 VOID
770 EnableorDisableTDShortPacket (
771 IN TD_STRUCT *PtrTDStruct,
772 IN BOOLEAN IsEnable
773 );
774
775 /**
776 Set the max error counter in TD.
777
778 @param PtrTDStruct Place to store TD_STRUCT pointer.
779 @param MaxErrors The number of allowable error.
780
781 **/
782 VOID
783 SetTDControlErrorCounter (
784 IN TD_STRUCT *PtrTDStruct,
785 IN UINT8 MaxErrors
786 );
787
788 /**
789 Set the TD is targeting a low-speed device or not.
790
791 @param PtrTDStruct Place to store TD_STRUCT pointer.
792 @param IsLowSpeedDevice Whether The device is low-speed.
793
794 **/
795 VOID
796 SetTDLoworFullSpeedDevice (
797 IN TD_STRUCT *PtrTDStruct,
798 IN BOOLEAN IsLowSpeedDevice
799 );
800
801 /**
802 Set the TD is isochronous transfer type or not.
803
804 @param PtrTDStruct Place to store TD_STRUCT pointer.
805 @param IsIsochronous Whether the transaction isochronous transfer type.
806
807 **/
808 VOID
809 SetTDControlIsochronousorNot (
810 IN TD_STRUCT *PtrTDStruct,
811 IN BOOLEAN IsIsochronous
812 );
813
814 /**
815 Set if UCHI should issue an interrupt on completion of the frame
816 in which this TD is executed
817
818 @param PtrTDStruct Place to store TD_STRUCT pointer.
819 @param IsSet Whether HC should issue an interrupt on completion.
820
821 **/
822 VOID
823 SetorClearTDControlIOC (
824 IN TD_STRUCT *PtrTDStruct,
825 IN BOOLEAN IsSet
826 );
827
828 /**
829 Set if the TD is active and can be executed.
830
831 @param PtrTDStruct Place to store TD_STRUCT pointer.
832 @param IsActive Whether the TD is active and can be executed.
833
834 **/
835 VOID
836 SetTDStatusActiveorInactive (
837 IN TD_STRUCT *PtrTDStruct,
838 IN BOOLEAN IsActive
839 );
840
841 /**
842 Specifies the maximum number of data bytes allowed for the transfer.
843
844 @param PtrTDStruct Place to store TD_STRUCT pointer.
845 @param MaxLen The maximum number of data bytes allowed.
846
847 @retval The allowed maximum number of data.
848 **/
849 UINT16
850 SetTDTokenMaxLength (
851 IN TD_STRUCT *PtrTDStruct,
852 IN UINT16 MaxLen
853 );
854
855 /**
856 Set the data toggle bit to DATA1.
857
858 @param PtrTDStruct Place to store TD_STRUCT pointer.
859
860 **/
861 VOID
862 SetTDTokenDataToggle1 (
863 IN TD_STRUCT *PtrTDStruct
864 );
865
866 /**
867 Set the data toggle bit to DATA0.
868
869 @param PtrTDStruct Place to store TD_STRUCT pointer.
870
871 **/
872 VOID
873 SetTDTokenDataToggle0 (
874 IN TD_STRUCT *PtrTDStruct
875 );
876
877 /**
878 Set EndPoint Number the TD is targeting at.
879
880 @param PtrTDStruct Place to store TD_STRUCT pointer.
881 @param EndPoint The Endport number of the target.
882
883 **/
884 VOID
885 SetTDTokenEndPoint (
886 IN TD_STRUCT *PtrTDStruct,
887 IN UINTN EndPoint
888 );
889
890 /**
891 Set Device Address the TD is targeting at.
892
893 @param PtrTDStruct Place to store TD_STRUCT pointer.
894 @param DevAddr The Device Address of the target.
895
896 **/
897 VOID
898 SetTDTokenDeviceAddress (
899 IN TD_STRUCT *PtrTDStruct,
900 IN UINTN DevAddr
901 );
902
903 /**
904 Set Packet Identification the TD is targeting at.
905
906 @param PtrTDStruct Place to store TD_STRUCT pointer.
907 @param PacketID The Packet Identification of the target.
908
909 **/
910 VOID
911 SetTDTokenPacketID (
912 IN TD_STRUCT *PtrTDStruct,
913 IN UINT8 PacketID
914 );
915
916 /**
917 Set the beginning address of the data buffer that will be used
918 during the transaction.
919
920 @param PtrTDStruct Place to store TD_STRUCT pointer.
921
922 **/
923 VOID
924 SetTDDataBuffer (
925 IN TD_STRUCT *PtrTDStruct
926 );
927
928 /**
929 Detect whether the TD is active.
930
931 @param PtrTDStruct Place to store TD_STRUCT pointer.
932
933 @retval The TD is active or not.
934
935 **/
936 BOOLEAN
937 IsTDStatusActive (
938 IN TD_STRUCT *PtrTDStruct
939 );
940
941 /**
942 Detect whether the TD is stalled.
943
944 @param PtrTDStruct Place to store TD_STRUCT pointer.
945
946 @retval The TD is stalled or not.
947
948 **/
949 BOOLEAN
950 IsTDStatusStalled (
951 IN TD_STRUCT *PtrTDStruct
952 );
953
954 /**
955 Detect whether Data Buffer Error is happened.
956
957 @param PtrTDStruct Place to store TD_STRUCT pointer.
958
959 @retval The Data Buffer Error is happened or not.
960
961 **/
962 BOOLEAN
963 IsTDStatusBufferError (
964 IN TD_STRUCT *PtrTDStruct
965 );
966
967 /**
968 Detect whether Babble Error is happened.
969
970 @param PtrTDStruct Place to store TD_STRUCT pointer.
971
972 @retval The Babble Error is happened or not.
973
974 **/
975 BOOLEAN
976 IsTDStatusBabbleError (
977 IN TD_STRUCT *PtrTDStruct
978 );
979
980 /**
981 Detect whether NAK is received.
982
983 @param PtrTDStruct Place to store TD_STRUCT pointer.
984
985 @retval The NAK is received or not.
986
987 **/
988 BOOLEAN
989 IsTDStatusNAKReceived (
990 IN TD_STRUCT *PtrTDStruct
991 );
992
993 /**
994 Detect whether CRC/Time Out Error is encountered.
995
996 @param PtrTDStruct Place to store TD_STRUCT pointer.
997
998 @retval The CRC/Time Out Error is encountered or not.
999
1000 **/
1001 BOOLEAN
1002 IsTDStatusCRCTimeOutError (
1003 IN TD_STRUCT *PtrTDStruct
1004 );
1005
1006 /**
1007 Detect whether Bitstuff Error is received.
1008
1009 @param PtrTDStruct Place to store TD_STRUCT pointer.
1010
1011 @retval The Bitstuff Error is received or not.
1012
1013 **/
1014 BOOLEAN
1015 IsTDStatusBitStuffError (
1016 IN TD_STRUCT *PtrTDStruct
1017 );
1018
1019 /**
1020 Retrieve the actual number of bytes that were tansferred.
1021
1022 @param PtrTDStruct Place to store TD_STRUCT pointer.
1023
1024 @retval The actual number of bytes that were tansferred.
1025
1026 **/
1027 UINT16
1028 GetTDStatusActualLength (
1029 IN TD_STRUCT *PtrTDStruct
1030 );
1031
1032 /**
1033 Retrieve the information of whether the Link Pointer field is valid or not.
1034
1035 @param PtrTDStruct Place to store TD_STRUCT pointer.
1036
1037 @retval The linker pointer field is valid or not.
1038
1039 **/
1040 BOOLEAN
1041 GetTDLinkPtrValidorInvalid (
1042 IN TD_STRUCT *PtrTDStruct
1043 );
1044
1045 /**
1046 Count TD Number from PtrFirstTD.
1047
1048 @param PtrFirstTD Place to store TD_STRUCT pointer.
1049
1050 @retval The queued TDs number.
1051
1052 **/
1053 UINTN
1054 CountTDsNumber (
1055 IN TD_STRUCT *PtrFirstTD
1056 );
1057
1058 /**
1059 Link TD To QH.
1060
1061 @param PtrQH Place to store QH_STRUCT pointer.
1062 @param PtrTD Place to store TD_STRUCT pointer.
1063
1064 **/
1065 VOID
1066 LinkTDToQH (
1067 IN QH_STRUCT *PtrQH,
1068 IN TD_STRUCT *PtrTD
1069 );
1070
1071 /**
1072 Link TD To TD.
1073
1074 @param PtrPreTD Place to store TD_STRUCT pointer.
1075 @param PtrTD Place to store TD_STRUCT pointer.
1076
1077 **/
1078 VOID
1079 LinkTDToTD (
1080 IN TD_STRUCT *PtrPreTD,
1081 IN TD_STRUCT *PtrTD
1082 );
1083
1084 /**
1085 Execute Control Transfer.
1086
1087 @param UhcDev The UCHI device.
1088 @param PtrTD A pointer to TD_STRUCT data.
1089 @param ActualLen Actual transfer Length.
1090 @param TimeOut TimeOut value.
1091 @param TransferResult Transfer Result.
1092
1093 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1094 @return EFI_TIMEOUT The transfer failed due to time out.
1095 @return EFI_SUCCESS The transfer finished OK.
1096
1097 **/
1098 EFI_STATUS
1099 ExecuteControlTransfer (
1100 IN USB_UHC_DEV *UhcDev,
1101 IN TD_STRUCT *PtrTD,
1102 OUT UINTN *ActualLen,
1103 IN UINTN TimeOut,
1104 OUT UINT32 *TransferResult
1105 );
1106
1107 /**
1108 Execute Bulk Transfer.
1109
1110 @param UhcDev The UCHI device.
1111 @param PtrTD A pointer to TD_STRUCT data.
1112 @param ActualLen Actual transfer Length.
1113 @param DataToggle DataToggle value.
1114 @param TimeOut TimeOut value.
1115 @param TransferResult Transfer Result.
1116
1117 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1118 @return EFI_TIMEOUT The transfer failed due to time out.
1119 @return EFI_SUCCESS The transfer finished OK.
1120
1121 **/
1122 EFI_STATUS
1123 ExecBulkTransfer (
1124 IN USB_UHC_DEV *UhcDev,
1125 IN TD_STRUCT *PtrTD,
1126 IN OUT UINTN *ActualLen,
1127 IN UINT8 *DataToggle,
1128 IN UINTN TimeOut,
1129 OUT UINT32 *TransferResult
1130 );
1131
1132 /**
1133 Delete Queued TDs.
1134
1135 @param UhcDev The UCHI device.
1136 @param PtrFirstTD Place to store TD_STRUCT pointer.
1137
1138 **/
1139 VOID
1140 DeleteQueuedTDs (
1141 IN USB_UHC_DEV *UhcDev,
1142 IN TD_STRUCT *PtrFirstTD
1143 );
1144
1145 /**
1146 Check TDs Results.
1147
1148 @param PtrTD A pointer to TD_STRUCT data.
1149 @param Result The result to return.
1150 @param ErrTDPos The Error TD position.
1151 @param ActualTransferSize Actual transfer size.
1152
1153 @retval The TD is executed successfully or not.
1154
1155 **/
1156 BOOLEAN
1157 CheckTDsResults (
1158 IN TD_STRUCT *PtrTD,
1159 OUT UINT32 *Result,
1160 OUT UINTN *ErrTDPos,
1161 OUT UINTN *ActualTransferSize
1162 );
1163
1164 /**
1165 Create Memory Block.
1166
1167 @param UhcDev The UCHI device.
1168 @param MemoryHeader The Pointer to allocated memory block.
1169 @param MemoryBlockSizeInPages The page size of memory block to be allocated.
1170
1171 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1172 @retval EFI_SUCCESS Success.
1173
1174 **/
1175 EFI_STATUS
1176 CreateMemoryBlock (
1177 IN USB_UHC_DEV *UhcDev,
1178 OUT MEMORY_MANAGE_HEADER **MemoryHeader,
1179 IN UINTN MemoryBlockSizeInPages
1180 );
1181
1182 /**
1183 Initialize UHCI memory management.
1184
1185 @param UhcDev The UCHI device.
1186
1187 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1188 @retval EFI_SUCCESS Success.
1189
1190 **/
1191 EFI_STATUS
1192 InitializeMemoryManagement (
1193 IN USB_UHC_DEV *UhcDev
1194 );
1195
1196 /**
1197 Initialize UHCI memory management.
1198
1199 @param UhcDev The UCHI device.
1200 @param Pool Buffer pointer to store the buffer pointer.
1201 @param AllocSize The size of the pool to be allocated.
1202
1203 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1204 @retval EFI_SUCCESS Success.
1205
1206 **/
1207 EFI_STATUS
1208 UhcAllocatePool (
1209 IN USB_UHC_DEV *UhcDev,
1210 OUT UINT8 **Pool,
1211 IN UINTN AllocSize
1212 );
1213
1214 /**
1215 Alloc Memory In MemoryBlock.
1216
1217 @param MemoryHeader The pointer to memory manage header.
1218 @param Pool Buffer pointer to store the buffer pointer.
1219 @param NumberOfMemoryUnit The size of the pool to be allocated.
1220
1221 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1222 @retval EFI_SUCCESS Success.
1223
1224 **/
1225 EFI_STATUS
1226 AllocMemInMemoryBlock (
1227 IN MEMORY_MANAGE_HEADER *MemoryHeader,
1228 OUT VOID **Pool,
1229 IN UINTN NumberOfMemoryUnit
1230 );
1231
1232 /**
1233 Uhci Free Pool.
1234
1235 @param UhcDev The UHCI device.
1236 @param Pool A pointer to store the buffer address.
1237 @param AllocSize The size of the pool to be freed.
1238
1239 **/
1240 VOID
1241 UhcFreePool (
1242 IN USB_UHC_DEV *UhcDev,
1243 IN UINT8 *Pool,
1244 IN UINTN AllocSize
1245 );
1246
1247 /**
1248 Insert a new memory header into list.
1249
1250 @param MemoryHeader A pointer to the memory header list.
1251 @param NewMemoryHeader A new memory header to be inserted into the list.
1252
1253 **/
1254 VOID
1255 InsertMemoryHeaderToList (
1256 IN MEMORY_MANAGE_HEADER *MemoryHeader,
1257 IN MEMORY_MANAGE_HEADER *NewMemoryHeader
1258 );
1259
1260
1261 /**
1262 Map address of request structure buffer.
1263
1264 @param Uhc The UHCI device.
1265 @param Request The user request buffer.
1266 @param MappedAddr Mapped address of request.
1267 @param Map Identificaion of this mapping to return.
1268
1269 @return EFI_SUCCESS Success.
1270 @return EFI_DEVICE_ERROR Fail to map the user request.
1271
1272 **/
1273 EFI_STATUS
1274 UhciMapUserRequest (
1275 IN USB_UHC_DEV *Uhc,
1276 IN OUT VOID *Request,
1277 OUT UINT8 **MappedAddr,
1278 OUT VOID **Map
1279 );
1280
1281 /**
1282 Map address of user data buffer.
1283
1284 @param Uhc The UHCI device.
1285 @param Direction Direction of the data transfer.
1286 @param Data The user data buffer.
1287 @param Len Length of the user data.
1288 @param PktId Packet identificaion.
1289 @param MappedAddr Mapped address to return.
1290 @param Map Identificaion of this mapping to return.
1291
1292 @return EFI_SUCCESS Success.
1293 @return EFI_DEVICE_ERROR Fail to map the user data.
1294
1295 **/
1296 EFI_STATUS
1297 UhciMapUserData (
1298 IN USB_UHC_DEV *Uhc,
1299 IN EFI_USB_DATA_DIRECTION Direction,
1300 IN VOID *Data,
1301 IN OUT UINTN *Len,
1302 OUT UINT8 *PktId,
1303 OUT UINT8 **MappedAddr,
1304 OUT VOID **Map
1305 );
1306
1307 /**
1308 Provides the controller-specific addresses required to access system memory from a
1309 DMA bus master.
1310
1311 @param IoMmu Pointer to IOMMU PPI.
1312 @param Operation Indicates if the bus master is going to read or write to system memory.
1313 @param HostAddress The system memory address to map to the PCI controller.
1314 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
1315 that were mapped.
1316 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
1317 access the hosts HostAddress.
1318 @param Mapping A resulting value to pass to Unmap().
1319
1320 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
1321 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1322 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1323 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1324 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
1325
1326 **/
1327 EFI_STATUS
1328 IoMmuMap (
1329 IN EDKII_IOMMU_PPI *IoMmu,
1330 IN EDKII_IOMMU_OPERATION Operation,
1331 IN VOID *HostAddress,
1332 IN OUT UINTN *NumberOfBytes,
1333 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
1334 OUT VOID **Mapping
1335 );
1336
1337 /**
1338 Completes the Map() operation and releases any corresponding resources.
1339
1340 @param IoMmu Pointer to IOMMU PPI.
1341 @param Mapping The mapping value returned from Map().
1342
1343 **/
1344 VOID
1345 IoMmuUnmap (
1346 IN EDKII_IOMMU_PPI *IoMmu,
1347 IN VOID *Mapping
1348 );
1349
1350 /**
1351 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
1352 OperationBusMasterCommonBuffer64 mapping.
1353
1354 @param IoMmu Pointer to IOMMU PPI.
1355 @param Pages The number of pages to allocate.
1356 @param HostAddress A pointer to store the base system memory address of the
1357 allocated range.
1358 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
1359 access the hosts HostAddress.
1360 @param Mapping A resulting value to pass to Unmap().
1361
1362 @retval EFI_SUCCESS The requested memory pages were allocated.
1363 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
1364 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
1365 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1366 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1367
1368 **/
1369 EFI_STATUS
1370 IoMmuAllocateBuffer (
1371 IN EDKII_IOMMU_PPI *IoMmu,
1372 IN UINTN Pages,
1373 OUT VOID **HostAddress,
1374 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
1375 OUT VOID **Mapping
1376 );
1377
1378
1379 /**
1380 Initialize IOMMU.
1381
1382 @param IoMmu Pointer to pointer to IOMMU PPI.
1383
1384 **/
1385 VOID
1386 IoMmuInit (
1387 OUT EDKII_IOMMU_PPI **IoMmu
1388 );
1389
1390 #endif