/** @file\r
The XHCI controller driver.\r
\r
-Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
-\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
// to the UEFI protocol's port state (change).\r
//\r
USB_PORT_STATE_MAP mUsbPortStateMap[] = {\r
- {XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION},\r
- {XHC_PORTSC_PED, USB_PORT_STAT_ENABLE},\r
- {XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},\r
- {XHC_PORTSC_RESET, USB_PORT_STAT_RESET}\r
+ { XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION },\r
+ { XHC_PORTSC_PED, USB_PORT_STAT_ENABLE },\r
+ { XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },\r
+ { XHC_PORTSC_RESET, USB_PORT_STAT_RESET }\r
};\r
\r
USB_PORT_STATE_MAP mUsbPortChangeMap[] = {\r
- {XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},\r
- {XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},\r
- {XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},\r
- {XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET}\r
+ { XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },\r
+ { XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },\r
+ { XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },\r
+ { XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET }\r
};\r
\r
-USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {\r
- {XHC_PORTSC_CSC, EfiUsbPortConnectChange},\r
- {XHC_PORTSC_PEC, EfiUsbPortEnableChange},\r
- {XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange},\r
- {XHC_PORTSC_PRC, EfiUsbPortResetChange}\r
+USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {\r
+ { XHC_PORTSC_CSC, EfiUsbPortConnectChange },\r
+ { XHC_PORTSC_PEC, EfiUsbPortEnableChange },\r
+ { XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange },\r
+ { XHC_PORTSC_PRC, EfiUsbPortResetChange }\r
};\r
\r
USB_PORT_STATE_MAP mUsbHubPortStateMap[] = {\r
- {XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION},\r
- {XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE},\r
- {XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},\r
- {XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET}\r
+ { XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION },\r
+ { XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE },\r
+ { XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT },\r
+ { XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET }\r
};\r
\r
USB_PORT_STATE_MAP mUsbHubPortChangeMap[] = {\r
- {XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},\r
- {XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},\r
- {XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},\r
- {XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET}\r
+ { XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION },\r
+ { XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE },\r
+ { XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT },\r
+ { XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET }\r
};\r
\r
-USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {\r
- {XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange},\r
- {XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange},\r
- {XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange},\r
- {XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange},\r
- {XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange}\r
+USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {\r
+ { XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange },\r
+ { XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange },\r
+ { XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange },\r
+ { XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange },\r
+ { XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange }\r
};\r
\r
EFI_DRIVER_BINDING_PROTOCOL gXhciDriverBinding = {\r
//\r
// Template for Xhci's Usb2 Host Controller Protocol Instance.\r
//\r
-EFI_USB2_HC_PROTOCOL gXhciUsb2HcTemplate = {\r
+EFI_USB2_HC_PROTOCOL gXhciUsb2HcTemplate = {\r
XhcGetCapability,\r
XhcReset,\r
XhcGetState,\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- OldTpl = gBS->RaiseTPL (XHC_TPL);\r
+ OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
Xhc = XHC_FROM_THIS (This);\r
*MaxSpeed = EFI_USB_SPEED_SUPER;\r
- *PortNumber = (UINT8) (Xhc->HcSParams1.Data.MaxPorts);\r
- *Is64BitCapable = (UINT8) Xhc->Support64BitDma;\r
- DEBUG ((EFI_D_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));\r
+ *PortNumber = (UINT8)(Xhc->HcSParams1.Data.MaxPorts);\r
+ *Is64BitCapable = (UINT8)Xhc->Support64BitDma;\r
+ DEBUG ((DEBUG_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable));\r
\r
gBS->RestoreTPL (OldTpl);\r
\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Provides software reset for the USB host controller.\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
switch (Attributes) {\r
- case EFI_USB_HC_RESET_GLOBAL:\r
- //\r
- // Flow through, same behavior as Host Controller Reset\r
- //\r
- case EFI_USB_HC_RESET_HOST_CONTROLLER:\r
- if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&\r
- ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {\r
- Status = EFI_SUCCESS;\r
- goto ON_EXIT;\r
- }\r
+ case EFI_USB_HC_RESET_GLOBAL:\r
//\r
- // Host Controller must be Halt when Reset it\r
+ // Flow through, same behavior as Host Controller Reset\r
//\r
- if (!XhcIsHalt (Xhc)) {\r
- Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);\r
+ case EFI_USB_HC_RESET_HOST_CONTROLLER:\r
+ if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&\r
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0))\r
+ {\r
+ Status = EFI_SUCCESS;\r
+ goto ON_EXIT;\r
+ }\r
+\r
+ //\r
+ // Host Controller must be Halt when Reset it\r
+ //\r
+ if (!XhcIsHalt (Xhc)) {\r
+ Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ goto ON_EXIT;\r
+ }\r
+ }\r
+\r
+ Status = XhcResetHC (Xhc, XHC_RESET_TIMEOUT);\r
+ ASSERT (!(XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_CNR)));\r
\r
if (EFI_ERROR (Status)) {\r
- Status = EFI_DEVICE_ERROR;\r
goto ON_EXIT;\r
}\r
- }\r
-\r
- Status = XhcResetHC (Xhc, XHC_RESET_TIMEOUT);\r
- ASSERT (!(XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_CNR)));\r
\r
- if (EFI_ERROR (Status)) {\r
- goto ON_EXIT;\r
- }\r
- //\r
- // Clean up the asynchronous transfers, currently only\r
- // interrupt supports asynchronous operation.\r
- //\r
- XhciDelAllAsyncIntTransfers (Xhc);\r
- XhcFreeSched (Xhc);\r
+ //\r
+ // Clean up the asynchronous transfers, currently only\r
+ // interrupt supports asynchronous operation.\r
+ //\r
+ XhciDelAllAsyncIntTransfers (Xhc);\r
+ XhcFreeSched (Xhc);\r
\r
- XhcInitSched (Xhc);\r
- break;\r
+ XhcInitSched (Xhc);\r
+ break;\r
\r
- case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:\r
- case EFI_USB_HC_RESET_HOST_WITH_DEBUG:\r
- Status = EFI_UNSUPPORTED;\r
- break;\r
+ case EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG:\r
+ case EFI_USB_HC_RESET_HOST_WITH_DEBUG:\r
+ Status = EFI_UNSUPPORTED;\r
+ break;\r
\r
- default:\r
- Status = EFI_INVALID_PARAMETER;\r
+ default:\r
+ Status = EFI_INVALID_PARAMETER;\r
}\r
\r
ON_EXIT:\r
- DEBUG ((EFI_D_INFO, "XhcReset: status %r\n", Status));\r
+ DEBUG ((DEBUG_INFO, "XhcReset: status %r\n", Status));\r
gBS->RestoreTPL (OldTpl);\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Retrieve the current state of the USB host controller.\r
\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
- Xhc = XHC_FROM_THIS (This);\r
+ Xhc = XHC_FROM_THIS (This);\r
\r
if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {\r
*State = EfiUsbHcStateHalt;\r
*State = EfiUsbHcStateOperational;\r
}\r
\r
- DEBUG ((EFI_D_INFO, "XhcGetState: current state %d\n", *State));\r
+ DEBUG ((DEBUG_INFO, "XhcGetState: current state %d\n", *State));\r
gBS->RestoreTPL (OldTpl);\r
\r
return EFI_SUCCESS;\r
IN EFI_USB_HC_STATE State\r
)\r
{\r
- USB_XHCI_INSTANCE *Xhc;\r
- EFI_STATUS Status;\r
- EFI_USB_HC_STATE CurState;\r
- EFI_TPL OldTpl;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ EFI_STATUS Status;\r
+ EFI_USB_HC_STATE CurState;\r
+ EFI_TPL OldTpl;\r
\r
Status = XhcGetState (This, &CurState);\r
\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
- Xhc = XHC_FROM_THIS (This);\r
+ Xhc = XHC_FROM_THIS (This);\r
\r
switch (State) {\r
- case EfiUsbHcStateHalt:\r
- Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);\r
- break;\r
-\r
- case EfiUsbHcStateOperational:\r
- if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE)) {\r
- Status = EFI_DEVICE_ERROR;\r
+ case EfiUsbHcStateHalt:\r
+ Status = XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);\r
break;\r
- }\r
\r
- //\r
- // Software must not write a one to this field unless the host controller\r
- // is in the Halted state. Doing so will yield undefined results.\r
- // refers to Spec[XHCI1.0-2.3.1]\r
- //\r
- if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {\r
- Status = EFI_DEVICE_ERROR;\r
- break;\r
- }\r
+ case EfiUsbHcStateOperational:\r
+ if (XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE)) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Software must not write a one to this field unless the host controller\r
+ // is in the Halted state. Doing so will yield undefined results.\r
+ // refers to Spec[XHCI1.0-2.3.1]\r
+ //\r
+ if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {\r
+ Status = EFI_DEVICE_ERROR;\r
+ break;\r
+ }\r
\r
- Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);\r
- break;\r
+ Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);\r
+ break;\r
\r
- case EfiUsbHcStateSuspend:\r
- Status = EFI_UNSUPPORTED;\r
- break;\r
+ case EfiUsbHcStateSuspend:\r
+ Status = EFI_UNSUPPORTED;\r
+ break;\r
\r
- default:\r
- Status = EFI_INVALID_PARAMETER;\r
+ default:\r
+ Status = EFI_INVALID_PARAMETER;\r
}\r
\r
- DEBUG ((EFI_D_INFO, "XhcSetState: status %r\n", Status));\r
+ DEBUG ((DEBUG_INFO, "XhcSetState: status %r\n", Status));\r
gBS->RestoreTPL (OldTpl);\r
\r
return Status;\r
OUT EFI_USB_PORT_STATUS *PortStatus\r
)\r
{\r
- USB_XHCI_INSTANCE *Xhc;\r
- UINT32 Offset;\r
- UINT32 State;\r
- UINT32 TotalPort;\r
- UINTN Index;\r
- UINTN MapSize;\r
- EFI_STATUS Status;\r
- USB_DEV_ROUTE ParentRouteChart;\r
- EFI_TPL OldTpl;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ UINT32 Offset;\r
+ UINT32 State;\r
+ UINT32 TotalPort;\r
+ UINTN Index;\r
+ UINTN MapSize;\r
+ UINT8 PortSpeed;\r
+ EFI_STATUS Status;\r
+ USB_DEV_ROUTE ParentRouteChart;\r
+ EFI_TPL OldTpl;\r
\r
if (PortStatus == NULL) {\r
return EFI_INVALID_PARAMETER;\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
- Xhc = XHC_FROM_THIS (This);\r
- Status = EFI_SUCCESS;\r
+ Xhc = XHC_FROM_THIS (This);\r
+ Status = EFI_SUCCESS;\r
\r
TotalPort = Xhc->HcSParams1.Data.MaxPorts;\r
\r
goto ON_EXIT;\r
}\r
\r
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r
PortStatus->PortStatus = 0;\r
PortStatus->PortChangeStatus = 0;\r
\r
State = XhcReadOpReg (Xhc, Offset);\r
\r
+ PortSpeed = (State & XHC_PORTSC_PS) >> 10;\r
+\r
//\r
- // According to XHCI 1.0 spec, bit 10~13 of the root port status register identifies the speed of the attached device.\r
+ // According to XHCI 1.1 spec November 2017,\r
+ // Section 7.2 xHCI Support Protocol Capability\r
//\r
- switch ((State & XHC_PORTSC_PS) >> 10) {\r
- case 2:\r
- PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;\r
- break;\r
-\r
- case 3:\r
- PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;\r
- break;\r
-\r
- case 4:\r
- PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;\r
- break;\r
-\r
- default:\r
- break;\r
+ if (PortSpeed > 0) {\r
+ PortStatus->PortStatus = XhcCheckUsbPortSpeedUsedPsic (Xhc, PortSpeed);\r
+ // If no match found in ext cap reg, fall back to PORTSC\r
+ if (PortStatus->PortStatus == 0) {\r
+ //\r
+ // According to XHCI 1.1 spec November 2017,\r
+ // bit 10~13 of the root port status register identifies the speed of the attached device.\r
+ //\r
+ switch (PortSpeed) {\r
+ case 2:\r
+ PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;\r
+ break;\r
+\r
+ case 3:\r
+ PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;\r
+ break;\r
+\r
+ case 4:\r
+ case 5:\r
+ PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ }\r
}\r
\r
//\r
\r
for (Index = 0; Index < MapSize; Index++) {\r
if (XHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {\r
- PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);\r
+ PortStatus->PortStatus = (UINT16)(PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);\r
}\r
}\r
+\r
//\r
// Bit5~8 reflects its current link state.\r
//\r
\r
for (Index = 0; Index < MapSize; Index++) {\r
if (XHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {\r
- PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);\r
+ PortStatus->PortChangeStatus = (UINT16)(PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);\r
}\r
}\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Sets a feature for the specified root hub port.\r
\r
IN EFI_USB_PORT_FEATURE PortFeature\r
)\r
{\r
- USB_XHCI_INSTANCE *Xhc;\r
- UINT32 Offset;\r
- UINT32 State;\r
- UINT32 TotalPort;\r
- EFI_STATUS Status;\r
- EFI_TPL OldTpl;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ UINT32 Offset;\r
+ UINT32 State;\r
+ UINT32 TotalPort;\r
+ EFI_STATUS Status;\r
+ EFI_TPL OldTpl;\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
goto ON_EXIT;\r
}\r
\r
- Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r
+ Offset = (UINT32)(XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r
State = XhcReadOpReg (Xhc, Offset);\r
\r
//\r
// Mask off the port status change bits, these bits are\r
// write clean bit\r
//\r
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);\r
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);\r
\r
switch (PortFeature) {\r
- case EfiUsbPortEnable:\r
- //\r
- // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.\r
- // A port may be disabled by software writing a '1' to this flag.\r
- //\r
- Status = EFI_SUCCESS;\r
- break;\r
-\r
- case EfiUsbPortSuspend:\r
- State |= XHC_PORTSC_LWS;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- State &= ~XHC_PORTSC_PLS;\r
- State |= (3 << 5) ;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- break;\r
-\r
- case EfiUsbPortReset:\r
- DEBUG ((EFI_D_INFO, "XhcUsbPortReset!\n"));\r
- //\r
- // Make sure Host Controller not halt before reset it\r
- //\r
- if (XhcIsHalt (Xhc)) {\r
- Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);\r
+ case EfiUsbPortEnable:\r
+ //\r
+ // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.\r
+ // A port may be disabled by software writing a '1' to this flag.\r
+ //\r
+ Status = EFI_SUCCESS;\r
+ break;\r
\r
- if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));\r
- break;\r
+ case EfiUsbPortSuspend:\r
+ State |= XHC_PORTSC_LWS;\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ State &= ~XHC_PORTSC_PLS;\r
+ State |= (3 << 5);\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ break;\r
+\r
+ case EfiUsbPortReset:\r
+ DEBUG ((DEBUG_INFO, "XhcUsbPortReset!\n"));\r
+ //\r
+ // Make sure Host Controller not halt before reset it\r
+ //\r
+ if (XhcIsHalt (Xhc)) {\r
+ Status = XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature :failed to start HC - %r\n", Status));\r
+ break;\r
+ }\r
}\r
- }\r
\r
- //\r
- // 4.3.1 Resetting a Root Hub Port\r
- // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.\r
- //\r
- State |= XHC_PORTSC_RESET;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- XhcWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);\r
- break;\r
+ //\r
+ // 4.3.1 Resetting a Root Hub Port\r
+ // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.\r
+ //\r
+ State |= XHC_PORTSC_RESET;\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);\r
+ break;\r
\r
- case EfiUsbPortPower:\r
- //\r
- // Not supported, ignore the operation\r
- //\r
- Status = EFI_SUCCESS;\r
- break;\r
+ case EfiUsbPortPower:\r
+ //\r
+ // Not supported, ignore the operation\r
+ //\r
+ Status = EFI_SUCCESS;\r
+ break;\r
\r
- case EfiUsbPortOwner:\r
- //\r
- // XHCI root hub port don't has the owner bit, ignore the operation\r
- //\r
- Status = EFI_SUCCESS;\r
- break;\r
+ case EfiUsbPortOwner:\r
+ //\r
+ // XHCI root hub port don't has the owner bit, ignore the operation\r
+ //\r
+ Status = EFI_SUCCESS;\r
+ break;\r
\r
- default:\r
- Status = EFI_INVALID_PARAMETER;\r
+ default:\r
+ Status = EFI_INVALID_PARAMETER;\r
}\r
\r
ON_EXIT:\r
- DEBUG ((EFI_D_INFO, "XhcSetRootHubPortFeature: status %r\n", Status));\r
+ DEBUG ((DEBUG_INFO, "XhcSetRootHubPortFeature: status %r\n", Status));\r
gBS->RestoreTPL (OldTpl);\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Clears a feature for the specified root hub port.\r
\r
IN EFI_USB_PORT_FEATURE PortFeature\r
)\r
{\r
- USB_XHCI_INSTANCE *Xhc;\r
- UINT32 Offset;\r
- UINT32 State;\r
- UINT32 TotalPort;\r
- EFI_STATUS Status;\r
- EFI_TPL OldTpl;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ UINT32 Offset;\r
+ UINT32 State;\r
+ UINT32 TotalPort;\r
+ EFI_STATUS Status;\r
+ EFI_TPL OldTpl;\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
- Xhc = XHC_FROM_THIS (This);\r
- Status = EFI_SUCCESS;\r
+ Xhc = XHC_FROM_THIS (This);\r
+ Status = EFI_SUCCESS;\r
\r
TotalPort = (Xhc->HcSParams1.Data.MaxPorts);\r
\r
// write clean bit\r
//\r
State = XhcReadOpReg (Xhc, Offset);\r
- State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);\r
+ State &= ~(BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);\r
\r
switch (PortFeature) {\r
- case EfiUsbPortEnable:\r
- //\r
- // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.\r
- // A port may be disabled by software writing a '1' to this flag.\r
- //\r
- State |= XHC_PORTSC_PED;\r
- State &= ~XHC_PORTSC_RESET;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- break;\r
-\r
- case EfiUsbPortSuspend:\r
- State |= XHC_PORTSC_LWS;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- State &= ~XHC_PORTSC_PLS;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- break;\r
-\r
- case EfiUsbPortReset:\r
- //\r
- // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:\r
- // Register bits indicate status when read, a clear bit may be set by\r
- // writing a '1'. Writing a '0' to RW1S bits has no effect.\r
- //\r
- break;\r
+ case EfiUsbPortEnable:\r
+ //\r
+ // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.\r
+ // A port may be disabled by software writing a '1' to this flag.\r
+ //\r
+ State |= XHC_PORTSC_PED;\r
+ State &= ~XHC_PORTSC_RESET;\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortOwner:\r
- //\r
- // XHCI root hub port don't has the owner bit, ignore the operation\r
- //\r
- break;\r
+ case EfiUsbPortSuspend:\r
+ State |= XHC_PORTSC_LWS;\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ State &= ~XHC_PORTSC_PLS;\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortConnectChange:\r
- //\r
- // Clear connect status change\r
- //\r
- State |= XHC_PORTSC_CSC;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- break;\r
+ case EfiUsbPortReset:\r
+ //\r
+ // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:\r
+ // Register bits indicate status when read, a clear bit may be set by\r
+ // writing a '1'. Writing a '0' to RW1S bits has no effect.\r
+ //\r
+ break;\r
\r
- case EfiUsbPortEnableChange:\r
- //\r
- // Clear enable status change\r
- //\r
- State |= XHC_PORTSC_PEC;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- break;\r
+ case EfiUsbPortOwner:\r
+ //\r
+ // XHCI root hub port don't has the owner bit, ignore the operation\r
+ //\r
+ break;\r
\r
- case EfiUsbPortOverCurrentChange:\r
- //\r
- // Clear PortOverCurrent change\r
- //\r
- State |= XHC_PORTSC_OCC;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- break;\r
+ case EfiUsbPortConnectChange:\r
+ //\r
+ // Clear connect status change\r
+ //\r
+ State |= XHC_PORTSC_CSC;\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortResetChange:\r
- //\r
- // Clear Port Reset change\r
- //\r
- State |= XHC_PORTSC_PRC;\r
- XhcWriteOpReg (Xhc, Offset, State);\r
- break;\r
+ case EfiUsbPortEnableChange:\r
+ //\r
+ // Clear enable status change\r
+ //\r
+ State |= XHC_PORTSC_PEC;\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ break;\r
\r
- case EfiUsbPortPower:\r
- case EfiUsbPortSuspendChange:\r
- //\r
- // Not supported or not related operation\r
- //\r
- break;\r
+ case EfiUsbPortOverCurrentChange:\r
+ //\r
+ // Clear PortOverCurrent change\r
+ //\r
+ State |= XHC_PORTSC_OCC;\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ break;\r
\r
- default:\r
- Status = EFI_INVALID_PARAMETER;\r
- break;\r
+ case EfiUsbPortResetChange:\r
+ //\r
+ // Clear Port Reset change\r
+ //\r
+ State |= XHC_PORTSC_PRC;\r
+ XhcWriteOpReg (Xhc, Offset, State);\r
+ break;\r
+\r
+ case EfiUsbPortPower:\r
+ case EfiUsbPortSuspendChange:\r
+ //\r
+ // Not supported or not related operation\r
+ //\r
+ break;\r
+\r
+ default:\r
+ Status = EFI_INVALID_PARAMETER;\r
+ break;\r
}\r
\r
ON_EXIT:\r
- DEBUG ((EFI_D_INFO, "XhcClearRootHubPortFeature: status %r\n", Status));\r
+ DEBUG ((DEBUG_INFO, "XhcClearRootHubPortFeature: status %r\n", Status));\r
gBS->RestoreTPL (OldTpl);\r
\r
return Status;\r
**/\r
EFI_STATUS\r
XhcTransfer (\r
- IN USB_XHCI_INSTANCE *Xhc,\r
- IN UINT8 DeviceAddress,\r
- IN UINT8 EndPointAddress,\r
- IN UINT8 DeviceSpeed,\r
- IN UINTN MaximumPacketLength,\r
- IN UINTN Type,\r
- IN EFI_USB_DEVICE_REQUEST *Request,\r
- IN OUT VOID *Data,\r
- IN OUT UINTN *DataLength,\r
- IN UINTN Timeout,\r
- OUT UINT32 *TransferResult\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 DeviceAddress,\r
+ IN UINT8 EndPointAddress,\r
+ IN UINT8 DeviceSpeed,\r
+ IN UINTN MaximumPacketLength,\r
+ IN UINTN Type,\r
+ IN EFI_USB_DEVICE_REQUEST *Request,\r
+ IN OUT VOID *Data,\r
+ IN OUT UINTN *DataLength,\r
+ IN UINTN Timeout,\r
+ OUT UINT32 *TransferResult\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_STATUS RecoveryStatus;\r
- URB *Urb;\r
+ EFI_STATUS Status;\r
+ EFI_STATUS RecoveryStatus;\r
+ URB *Urb;\r
\r
ASSERT ((Type == XHC_CTRL_TRANSFER) || (Type == XHC_BULK_TRANSFER) || (Type == XHC_INT_TRANSFER_SYNC));\r
Urb = XhcCreateUrb (\r
//\r
// The transfer timed out. Abort the transfer by dequeueing of the TD.\r
//\r
- RecoveryStatus = XhcDequeueTrbFromEndpoint(Xhc, Urb);\r
+ RecoveryStatus = XhcDequeueTrbFromEndpoint (Xhc, Urb);\r
if (RecoveryStatus == EFI_ALREADY_STARTED) {\r
//\r
// The URB is finished just before stopping endpoint.\r
ASSERT (Urb->Result == EFI_USB_NOERROR);\r
Status = EFI_SUCCESS;\r
DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: pending URB is finished, Length = %d.\n", Type, Urb->Completed));\r
- } else if (EFI_ERROR(RecoveryStatus)) {\r
- DEBUG((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcDequeueTrbFromEndpoint failed!\n", Type));\r
+ } else if (EFI_ERROR (RecoveryStatus)) {\r
+ DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcDequeueTrbFromEndpoint failed!\n", Type));\r
}\r
}\r
\r
\r
if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {\r
ASSERT (Status == EFI_DEVICE_ERROR);\r
- RecoveryStatus = XhcRecoverHaltedEndpoint(Xhc, Urb);\r
+ RecoveryStatus = XhcRecoverHaltedEndpoint (Xhc, Urb);\r
if (EFI_ERROR (RecoveryStatus)) {\r
DEBUG ((DEBUG_ERROR, "XhcTransfer[Type=%d]: XhcRecoverHaltedEndpoint failed!\n", Type));\r
}\r
\r
if ((TransferDirection != EfiUsbDataIn) &&\r
(TransferDirection != EfiUsbDataOut) &&\r
- (TransferDirection != EfiUsbNoData)) {\r
+ (TransferDirection != EfiUsbNoData))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if ((TransferDirection == EfiUsbNoData) &&\r
- ((Data != NULL) || (*DataLength != 0))) {\r
+ ((Data != NULL) || (*DataLength != 0)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if ((TransferDirection != EfiUsbNoData) &&\r
- ((Data == NULL) || (*DataLength == 0))) {\r
+ ((Data == NULL) || (*DataLength == 0)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&\r
(MaximumPacketLength != 32) && (MaximumPacketLength != 64) &&\r
(MaximumPacketLength != 512)\r
- ) {\r
+ )\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
- Xhc = XHC_FROM_THIS (This);\r
+ Xhc = XHC_FROM_THIS (This);\r
\r
Status = EFI_DEVICE_ERROR;\r
*TransferResult = EFI_USB_ERR_SYSTEM;\r
Len = 0;\r
\r
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r
- DEBUG ((EFI_D_ERROR, "XhcControlTransfer: HC halted at entrance\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcControlTransfer: HC halted at entrance\n"));\r
goto ON_EXIT;\r
}\r
\r
// According to XHCI 1.0 spec, the Set_Address request is replaced by XHCI's Address_Device cmd.\r
//\r
if ((Request->Request == USB_REQ_SET_ADDRESS) &&\r
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {\r
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))\r
+ {\r
//\r
// Reset the BusDevAddr field of all disabled entries in UsbDevContext array firstly.\r
// This way is used to clean the history to avoid using wrong device address by XhcAsyncInterruptTransfer().\r
for (Index = 0; Index < 255; Index++) {\r
if (!Xhc->UsbDevContext[Index + 1].Enabled &&\r
(Xhc->UsbDevContext[Index + 1].SlotId == 0) &&\r
- (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value)) {\r
+ (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8)Request->Value))\r
+ {\r
Xhc->UsbDevContext[Index + 1].BusDevAddr = 0;\r
}\r
}\r
Status = EFI_DEVICE_ERROR;\r
goto ON_EXIT;\r
}\r
+\r
//\r
// The actual device address has been assigned by XHCI during initializing the device slot.\r
// So we just need establish the mapping relationship between the device address requested from UsbBus\r
// can find out the actual device address by it.\r
//\r
Xhc->UsbDevContext[SlotId].BusDevAddr = (UINT8)Request->Value;\r
- Status = EFI_SUCCESS;\r
+ Status = EFI_SUCCESS;\r
goto ON_EXIT;\r
}\r
\r
// endpoint is bidirectional. XhcCreateUrb expects this\r
// combination of Ep addr and its direction.\r
//\r
- Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));\r
- Status = XhcTransfer (\r
- Xhc,\r
- DeviceAddress,\r
- Endpoint,\r
- DeviceSpeed,\r
- MaximumPacketLength,\r
- XHC_CTRL_TRANSFER,\r
- Request,\r
- Data,\r
- DataLength,\r
- Timeout,\r
- TransferResult\r
- );\r
+ Endpoint = (UINT8)(0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));\r
+ Status = XhcTransfer (\r
+ Xhc,\r
+ DeviceAddress,\r
+ Endpoint,\r
+ DeviceSpeed,\r
+ MaximumPacketLength,\r
+ XHC_CTRL_TRANSFER,\r
+ Request,\r
+ Data,\r
+ DataLength,\r
+ Timeout,\r
+ TransferResult\r
+ );\r
\r
if (EFI_ERROR (Status)) {\r
goto ON_EXIT;\r
//\r
if ((Request->Request == USB_REQ_GET_DESCRIPTOR) &&\r
((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||\r
- ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {\r
+ ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE)))))\r
+ {\r
DescriptorType = (UINT8)(Request->Value >> 8);\r
if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {\r
- ASSERT (Data != NULL);\r
+ ASSERT (Data != NULL);\r
+ //\r
+ // Store a copy of device scriptor as hub device need this info to configure endpoint.\r
+ //\r
+ CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);\r
+ if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {\r
//\r
- // Store a copy of device scriptor as hub device need this info to configure endpoint.\r
+ // If it's a usb3.0 device, then its max packet size is a 2^n.\r
//\r
- CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);\r
- if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {\r
- //\r
- // If it's a usb3.0 device, then its max packet size is a 2^n.\r
- //\r
- MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;\r
- } else {\r
- MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;\r
- }\r
- Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));\r
- if (Xhc->HcCParams.Data.Csz == 0) {\r
- Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);\r
- } else {\r
- Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);\r
- }\r
+ MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;\r
+ } else {\r
+ MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;\r
+ }\r
+\r
+ Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));\r
+ if (Xhc->HcCParams.Data.Csz == 0) {\r
+ Status = XhcEvaluateContext (Xhc, SlotId, MaxPacket0);\r
+ } else {\r
+ Status = XhcEvaluateContext64 (Xhc, SlotId, MaxPacket0);\r
+ }\r
} else if (DescriptorType == USB_DESC_TYPE_CONFIG) {\r
ASSERT (Data != NULL);\r
if (*DataLength == ((UINT16 *)Data)[1]) {\r
//\r
Index = (UINT8)Request->Value;\r
ASSERT (Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations);\r
- Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool(*DataLength);\r
+ Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool (*DataLength);\r
CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);\r
//\r
// Default to use AlternateSetting 0 for all interfaces.\r
Xhc->UsbDevContext[SlotId].ActiveAlternateSetting = AllocateZeroPool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]->NumInterfaces * sizeof (UINT8));\r
}\r
} else if (((DescriptorType == USB_DESC_TYPE_HUB) ||\r
- (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2)) {\r
+ (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2))\r
+ {\r
ASSERT (Data != NULL);\r
HubDesc = (EFI_USB_HUB_DESCRIPTOR *)Data;\r
ASSERT (HubDesc->NumPorts <= 15);\r
// Don't support multi-TT feature for super speed hub now.\r
//\r
MTT = 0;\r
- DEBUG ((EFI_D_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));\r
+ DEBUG ((DEBUG_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));\r
} else {\r
MTT = 0;\r
}\r
}\r
}\r
} else if ((Request->Request == USB_REQ_SET_CONFIG) &&\r
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {\r
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)))\r
+ {\r
//\r
// Hook Set_Config request from UsbBus as we need configure device endpoint.\r
//\r
} else {\r
Status = XhcSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r
}\r
+\r
break;\r
}\r
}\r
} else if ((Request->Request == USB_REQ_SET_INTERFACE) &&\r
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_INTERFACE))) {\r
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_INTERFACE)))\r
+ {\r
//\r
// Hook Set_Interface request from UsbBus as we need configure interface setting.\r
// Request->Value indicates AlterlateSetting to set\r
// Request->Index indicates Interface to set\r
//\r
- if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8) Request->Index] != (UINT8) Request->Value) {\r
+ if (Xhc->UsbDevContext[SlotId].ActiveAlternateSetting[(UINT8)Request->Index] != (UINT8)Request->Value) {\r
if (Xhc->HcCParams.Data.Csz == 0) {\r
Status = XhcSetInterface (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Xhc->UsbDevContext[SlotId].ActiveConfiguration - 1], Request);\r
} else {\r
}\r
}\r
} else if ((Request->Request == USB_REQ_GET_STATUS) &&\r
- (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER))) {\r
+ (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER)))\r
+ {\r
ASSERT (Data != NULL);\r
//\r
// Hook Get_Status request from UsbBus to keep track of the port status change.\r
MapSize = sizeof (mUsbHubPortStateMap) / sizeof (USB_PORT_STATE_MAP);\r
for (Index = 0; Index < MapSize; Index++) {\r
if (XHC_BIT_IS_SET (State, mUsbHubPortStateMap[Index].HwState)) {\r
- PortStatus.PortStatus = (UINT16) (PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);\r
+ PortStatus.PortStatus = (UINT16)(PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);\r
}\r
}\r
\r
MapSize = sizeof (mUsbHubPortChangeMap) / sizeof (USB_PORT_STATE_MAP);\r
for (Index = 0; Index < MapSize; Index++) {\r
if (XHC_BIT_IS_SET (State, mUsbHubPortChangeMap[Index].HwState)) {\r
- PortStatus.PortChangeStatus = (UINT16) (PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);\r
+ PortStatus.PortChangeStatus = (UINT16)(PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);\r
}\r
}\r
\r
for (Index = 0; Index < MapSize; Index++) {\r
if (XHC_BIT_IS_SET (State, mUsbHubClearPortChangeMap[Index].HwState)) {\r
ZeroMem (&ClearPortRequest, sizeof (EFI_USB_DEVICE_REQUEST));\r
- ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);\r
- ClearPortRequest.Request = (UINT8) USB_REQ_CLEAR_FEATURE;\r
- ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;\r
- ClearPortRequest.Index = Request->Index;\r
- ClearPortRequest.Length = 0;\r
+ ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);\r
+ ClearPortRequest.Request = (UINT8)USB_REQ_CLEAR_FEATURE;\r
+ ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;\r
+ ClearPortRequest.Index = Request->Index;\r
+ ClearPortRequest.Length = 0;\r
\r
XhcControlTransfer (\r
This,\r
\r
XhcPollPortStatusChange (Xhc, Xhc->UsbDevContext[SlotId].RouteString, (UINT8)Request->Index, &PortStatus);\r
\r
- *(UINT32 *)Data = *(UINT32*)&PortStatus;\r
+ *(UINT32 *)Data = *(UINT32 *)&PortStatus;\r
}\r
\r
ON_EXIT:\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r
+ DEBUG ((DEBUG_ERROR, "XhcControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r
}\r
\r
gBS->RestoreTPL (OldTpl);\r
return Status;\r
}\r
\r
-\r
/**\r
Submits bulk transfer to a bulk endpoint of a USB device.\r
\r
OUT UINT32 *TransferResult\r
)\r
{\r
- USB_XHCI_INSTANCE *Xhc;\r
- UINT8 SlotId;\r
- EFI_STATUS Status;\r
- EFI_TPL OldTpl;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ UINT8 SlotId;\r
+ EFI_STATUS Status;\r
+ EFI_TPL OldTpl;\r
+ UINTN DebugErrorLevel;\r
\r
//\r
// Validate the parameters\r
//\r
if ((DataLength == NULL) || (*DataLength == 0) ||\r
- (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {\r
+ (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||\r
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||\r
((EFI_USB_SPEED_HIGH == DeviceSpeed) && (MaximumPacketLength > 512)) ||\r
- ((EFI_USB_SPEED_SUPER == DeviceSpeed) && (MaximumPacketLength > 1024))) {\r
+ ((EFI_USB_SPEED_SUPER == DeviceSpeed) && (MaximumPacketLength > 1024)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
- Xhc = XHC_FROM_THIS (This);\r
+ Xhc = XHC_FROM_THIS (This);\r
\r
*TransferResult = EFI_USB_ERR_SYSTEM;\r
Status = EFI_DEVICE_ERROR;\r
\r
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r
- DEBUG ((EFI_D_ERROR, "XhcBulkTransfer: HC is halted\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcBulkTransfer: HC is halted\n"));\r
goto ON_EXIT;\r
}\r
\r
\r
ON_EXIT:\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r
+ if (Status == EFI_TIMEOUT) {\r
+ DebugErrorLevel = DEBUG_VERBOSE;\r
+ } else {\r
+ DebugErrorLevel = DEBUG_ERROR;\r
+ }\r
+\r
+ DEBUG ((DebugErrorLevel, "XhcBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r
}\r
+\r
gBS->RestoreTPL (OldTpl);\r
\r
return Status;\r
IN VOID *Context OPTIONAL\r
)\r
{\r
- USB_XHCI_INSTANCE *Xhc;\r
- URB *Urb;\r
- EFI_STATUS Status;\r
- UINT8 SlotId;\r
- UINT8 Index;\r
- UINT8 *Data;\r
- EFI_TPL OldTpl;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ URB *Urb;\r
+ EFI_STATUS Status;\r
+ UINT8 SlotId;\r
+ UINT8 Index;\r
+ EFI_TPL OldTpl;\r
\r
//\r
// Validate parameters\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
- Xhc = XHC_FROM_THIS (This);\r
+ Xhc = XHC_FROM_THIS (This);\r
\r
//\r
// Delete Async interrupt transfer request.\r
}\r
\r
Status = XhciDelAsyncIntTransfer (Xhc, DeviceAddress, EndPointAddress);\r
- DEBUG ((EFI_D_INFO, "XhcAsyncInterruptTransfer: remove old transfer for addr %d, Status = %r\n", DeviceAddress, Status));\r
+ DEBUG ((DEBUG_INFO, "XhcAsyncInterruptTransfer: remove old transfer for addr %d, Status = %r\n", DeviceAddress, Status));\r
goto ON_EXIT;\r
}\r
\r
Status = EFI_SUCCESS;\r
\r
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r
- DEBUG ((EFI_D_ERROR, "XhcAsyncInterruptTransfer: HC is halt\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcAsyncInterruptTransfer: HC is halt\n"));\r
Status = EFI_DEVICE_ERROR;\r
goto ON_EXIT;\r
}\r
goto ON_EXIT;\r
}\r
\r
- Data = AllocateZeroPool (DataLength);\r
-\r
- if (Data == NULL) {\r
- DEBUG ((EFI_D_ERROR, "XhcAsyncInterruptTransfer: failed to allocate buffer\n"));\r
- Status = EFI_OUT_OF_RESOURCES;\r
- goto ON_EXIT;\r
- }\r
-\r
- Urb = XhcCreateUrb (\r
+ Urb = XhciInsertAsyncIntTransfer (\r
Xhc,\r
DeviceAddress,\r
EndPointAddress,\r
DeviceSpeed,\r
MaximumPacketLength,\r
- XHC_INT_TRANSFER_ASYNC,\r
- NULL,\r
- Data,\r
DataLength,\r
CallBackFunction,\r
Context\r
);\r
-\r
if (Urb == NULL) {\r
- DEBUG ((EFI_D_ERROR, "XhcAsyncInterruptTransfer: failed to create URB\n"));\r
- FreePool (Data);\r
Status = EFI_OUT_OF_RESOURCES;\r
goto ON_EXIT;\r
}\r
\r
- InsertHeadList (&Xhc->AsyncIntTransfers, &Urb->UrbList);\r
//\r
// Ring the doorbell\r
//\r
return Status;\r
}\r
\r
-\r
/**\r
Submits synchronous interrupt transfer to an interrupt endpoint\r
of a USB device.\r
OUT UINT32 *TransferResult\r
)\r
{\r
- USB_XHCI_INSTANCE *Xhc;\r
- UINT8 SlotId;\r
- EFI_STATUS Status;\r
- EFI_TPL OldTpl;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ UINT8 SlotId;\r
+ EFI_STATUS Status;\r
+ EFI_TPL OldTpl;\r
\r
//\r
// Validates parameters\r
//\r
if ((DataLength == NULL) || (*DataLength == 0) ||\r
- (Data == NULL) || (TransferResult == NULL)) {\r
+ (Data == NULL) || (TransferResult == NULL))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
\r
if (((DeviceSpeed == EFI_USB_SPEED_LOW) && (MaximumPacketLength != 8)) ||\r
((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||\r
- ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072))) {\r
+ ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 3072)))\r
+ {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
OldTpl = gBS->RaiseTPL (XHC_TPL);\r
\r
- Xhc = XHC_FROM_THIS (This);\r
+ Xhc = XHC_FROM_THIS (This);\r
\r
*TransferResult = EFI_USB_ERR_SYSTEM;\r
Status = EFI_DEVICE_ERROR;\r
\r
if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r
- DEBUG ((EFI_D_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));\r
+ DEBUG ((DEBUG_ERROR, "EhcSyncInterruptTransfer: HC is halt\n"));\r
goto ON_EXIT;\r
}\r
\r
\r
ON_EXIT:\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r
+ DEBUG ((DEBUG_ERROR, "XhcSyncInterruptTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r
}\r
+\r
gBS->RestoreTPL (OldTpl);\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Submits isochronous transfer to a target USB device.\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
-\r
/**\r
Submits Async isochronous transfer to a target USB device.\r
\r
EFI_STATUS\r
EFIAPI\r
XhcDriverEntryPoint (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
return EfiLibInstallDriverBindingComponentName2 (\r
);\r
}\r
\r
-\r
/**\r
Test to see if this driver supports ControllerHandle. Any\r
ControllerHandle that has Usb2HcProtocol installed will\r
EFI_STATUS\r
EFIAPI\r
XhcDriverBindingSupported (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
- IN EFI_HANDLE Controller,\r
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- USB_CLASSC UsbClassCReg;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ USB_CLASSC UsbClassCReg;\r
\r
//\r
// Test whether there is PCI IO Protocol attached on the controller handle.\r
Status = gBS->OpenProtocol (\r
Controller,\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo,\r
+ (VOID **)&PciIo,\r
This->DriverBindingHandle,\r
Controller,\r
EFI_OPEN_PROTOCOL_BY_DRIVER\r
//\r
if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) ||\r
(UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) ||\r
- (UsbClassCReg.ProgInterface != PCI_IF_XHCI)) {\r
+ (UsbClassCReg.ProgInterface != PCI_IF_XHCI))\r
+ {\r
Status = EFI_UNSUPPORTED;\r
}\r
\r
otherwise NULL.\r
\r
**/\r
-USB_XHCI_INSTANCE*\r
+USB_XHCI_INSTANCE *\r
XhcCreateUsbHc (\r
IN EFI_PCI_IO_PROTOCOL *PciIo,\r
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
IN UINT64 OriginalPciAttributes\r
)\r
{\r
- USB_XHCI_INSTANCE *Xhc;\r
- EFI_STATUS Status;\r
- UINT32 PageSize;\r
- UINT16 ExtCapReg;\r
- UINT8 ReleaseNumber;\r
+ USB_XHCI_INSTANCE *Xhc;\r
+ EFI_STATUS Status;\r
+ UINT32 PageSize;\r
+ UINT16 ExtCapReg;\r
+ UINT8 ReleaseNumber;\r
\r
Xhc = AllocateZeroPool (sizeof (USB_XHCI_INSTANCE));\r
\r
// This xHC supports a page size of 2^(n+12) if bit n is Set. For example,\r
// if bit 0 is Set, the xHC supports 4k byte page sizes.\r
//\r
- PageSize = XhcReadOpReg(Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;\r
- Xhc->PageSize = 1 << (HighBitSet32(PageSize) + 12);\r
+ PageSize = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET);\r
+ if ((PageSize & (~XHC_PAGESIZE_MASK)) != 0) {\r
+ DEBUG ((DEBUG_ERROR, "XhcCreateUsb3Hc: Reserved bits are not 0 for PageSize\n"));\r
+ goto ON_ERROR;\r
+ }\r
\r
- ExtCapReg = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);\r
- Xhc->ExtCapRegBase = ExtCapReg << 2;\r
- Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);\r
+ PageSize &= XHC_PAGESIZE_MASK;\r
+ Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12);\r
+\r
+ ExtCapReg = (UINT16)(Xhc->HcCParams.Data.ExtCapReg);\r
+ Xhc->ExtCapRegBase = ExtCapReg << 2;\r
+ Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);\r
Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);\r
+ Xhc->Usb2SupOffset = XhcGetSupportedProtocolCapabilityAddr (Xhc, XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2);\r
+ Xhc->Usb3SupOffset = XhcGetSupportedProtocolCapabilityAddr (Xhc, XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3);\r
\r
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));\r
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));\r
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams2 0x%x\n", Xhc->HcSParams2));\r
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcCParams 0x%x\n", Xhc->HcCParams));\r
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));\r
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));\r
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));\r
- DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcSParams2 0x%x\n", Xhc->HcSParams2));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: HcCParams 0x%x\n", Xhc->HcCParams));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Usb2SupOffset 0x%x\n", Xhc->Usb2SupOffset));\r
+ DEBUG ((DEBUG_INFO, "XhcCreateUsb3Hc: Usb3SupOffset 0x%x\n", Xhc->Usb3SupOffset));\r
\r
//\r
// Create AsyncRequest Polling Timer\r
USB_XHCI_INSTANCE *Xhc;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
\r
- Xhc = (USB_XHCI_INSTANCE*) Context;\r
+ Xhc = (USB_XHCI_INSTANCE *)Context;\r
PciIo = Xhc->PciIo;\r
\r
//\r
// Restore original PCI attributes\r
//\r
PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationSet,\r
- Xhc->OriginalPciAttributes,\r
- NULL\r
- );\r
+ PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ Xhc->OriginalPciAttributes,\r
+ NULL\r
+ );\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
XhcDriverBindingStart (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
- IN EFI_HANDLE Controller,\r
- IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PCI_IO_PROTOCOL *PciIo;\r
- UINT64 Supports;\r
- UINT64 OriginalPciAttributes;\r
- BOOLEAN PciAttributesSaved;\r
- USB_XHCI_INSTANCE *Xhc;\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINT64 Supports;\r
+ UINT64 OriginalPciAttributes;\r
+ BOOLEAN PciAttributesSaved;\r
+ USB_XHCI_INSTANCE *Xhc;\r
EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;\r
\r
//\r
Status = gBS->OpenProtocol (\r
Controller,\r
&gEfiPciIoProtocolGuid,\r
- (VOID **) &PciIo,\r
+ (VOID **)&PciIo,\r
This->DriverBindingHandle,\r
Controller,\r
EFI_OPEN_PROTOCOL_BY_DRIVER\r
// Open Device Path Protocol for on USB host controller\r
//\r
HcDevicePath = NULL;\r
- Status = gBS->OpenProtocol (\r
- Controller,\r
- &gEfiDevicePathProtocolGuid,\r
- (VOID **) &HcDevicePath,\r
- This->DriverBindingHandle,\r
- Controller,\r
- EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
- );\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **)&HcDevicePath,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+ );\r
\r
PciAttributesSaved = FALSE;\r
//\r
if (EFI_ERROR (Status)) {\r
goto CLOSE_PCIIO;\r
}\r
+\r
PciAttributesSaved = TRUE;\r
\r
Status = PciIo->Attributes (\r
);\r
if (!EFI_ERROR (Status)) {\r
Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r
- Status = PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationEnable,\r
- Supports,\r
- NULL\r
- );\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationEnable,\r
+ Supports,\r
+ NULL\r
+ );\r
}\r
\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to enable controller\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to enable controller\n"));\r
goto CLOSE_PCIIO;\r
}\r
\r
Xhc = XhcCreateUsbHc (PciIo, HcDevicePath, OriginalPciAttributes);\r
\r
if (Xhc == NULL) {\r
- DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to create USB2_HC\n"));\r
return EFI_OUT_OF_RESOURCES;\r
}\r
\r
if (!EFI_ERROR (Status)) {\r
Xhc->Support64BitDma = TRUE;\r
} else {\r
- DEBUG ((EFI_D_WARN,\r
+ DEBUG ((\r
+ DEBUG_WARN,\r
"%a: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n",\r
- __FUNCTION__, Controller, Status));\r
+ __FUNCTION__,\r
+ Controller,\r
+ Status\r
+ ));\r
}\r
}\r
\r
//\r
// Start the Host Controller\r
//\r
- XhcRunHC(Xhc, XHC_GENERIC_TIMEOUT);\r
+ XhcRunHC (Xhc, XHC_GENERIC_TIMEOUT);\r
\r
//\r
// Start the asynchronous interrupt monitor\r
//\r
Status = gBS->SetTimer (Xhc->PollTimer, TimerPeriodic, XHC_ASYNC_TIMER_INTERVAL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to start async interrupt monitor\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to start async interrupt monitor\n"));\r
XhcHaltHC (Xhc, XHC_GENERIC_TIMEOUT);\r
goto FREE_POOL;\r
}\r
&Xhc->Usb2Hc\r
);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((EFI_D_ERROR, "XhcDriverBindingStart: failed to install USB2_HC Protocol\n"));\r
+ DEBUG ((DEBUG_ERROR, "XhcDriverBindingStart: failed to install USB2_HC Protocol\n"));\r
goto FREE_POOL;\r
}\r
\r
- DEBUG ((EFI_D_INFO, "XhcDriverBindingStart: XHCI started for controller @ %x\n", Controller));\r
+ DEBUG ((DEBUG_INFO, "XhcDriverBindingStart: XHCI started for controller @ %x\n", Controller));\r
return EFI_SUCCESS;\r
\r
FREE_POOL:\r
// Restore original PCI attributes\r
//\r
PciIo->Attributes (\r
- PciIo,\r
- EfiPciIoAttributeOperationSet,\r
- OriginalPciAttributes,\r
- NULL\r
- );\r
+ PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ OriginalPciAttributes,\r
+ NULL\r
+ );\r
}\r
\r
gBS->CloseProtocol (\r
return Status;\r
}\r
\r
-\r
/**\r
Stop this driver on ControllerHandle. Support stopping any child handles\r
created by this driver.\r
EFI_STATUS\r
EFIAPI\r
XhcDriverBindingStop (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
- IN EFI_HANDLE Controller,\r
- IN UINTN NumberOfChildren,\r
- IN EFI_HANDLE *ChildHandleBuffer\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN UINTN NumberOfChildren,\r
+ IN EFI_HANDLE *ChildHandleBuffer\r
)\r
{\r
EFI_STATUS Status;\r
Status = gBS->OpenProtocol (\r
Controller,\r
&gEfiUsb2HcProtocolGuid,\r
- (VOID **) &Usb2Hc,\r
+ (VOID **)&Usb2Hc,\r
This->DriverBindingHandle,\r
Controller,\r
EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
//\r
for (Index = 0; Index < 255; Index++) {\r
if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r
- (Xhc->UsbDevContext[Index + 1].SlotId == 0)) {\r
+ (Xhc->UsbDevContext[Index + 1].SlotId == 0))\r
+ {\r
continue;\r
}\r
+\r
if (Xhc->HcCParams.Data.Csz == 0) {\r
XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r
} else {\r
\r
return EFI_SUCCESS;\r
}\r
-\r
projects / mirror_edk2.git / blobdiff