MdeModulePkg UhciPei: Remove redundant functions

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.c

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index a513dd958104ac0daa674c6054a3ba8f3035cb00..4d5937de538f8b907c44ec5ecf1a002a44ef3cfc 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -2,7 +2,7 @@
 \r
   The XHCI register operation routines.\r
 \r
-Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -112,7 +112,7 @@ XhcReadOpReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->CapLength + Offset),\r
+                             Xhc->CapLength + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -148,7 +148,7 @@ XhcWriteOpReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->CapLength + Offset),\r
+                             Xhc->CapLength + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -181,7 +181,7 @@ XhcWriteOpReg16 (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint16,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->CapLength + Offset),\r
+                             Xhc->CapLength + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -215,7 +215,7 @@ XhcReadDoorBellReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->DBOff + Offset),\r
+                             Xhc->DBOff + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -251,7 +251,7 @@ XhcWriteDoorBellReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->DBOff + Offset),\r
+                             Xhc->DBOff + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -285,7 +285,7 @@ XhcReadRuntimeReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->RTSOff + Offset),\r
+                             Xhc->RTSOff + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -321,7 +321,7 @@ XhcWriteRuntimeReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->RTSOff + Offset),\r
+                             Xhc->RTSOff + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -355,7 +355,7 @@ XhcReadExtCapReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->ExtCapRegBase + Offset),\r
+                             Xhc->ExtCapRegBase + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -391,7 +391,7 @@ XhcWriteExtCapReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->ExtCapRegBase + Offset),\r
+                             Xhc->ExtCapRegBase + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -499,7 +499,7 @@ XhcClearOpRegBit (
   @param  Offset       The offset of the operation register.\r
   @param  Bit          The bit of the register to wait for.\r
   @param  WaitToSet    Wait the bit to set or clear.\r
-  @param  Timeout      The time to wait before abort (in microsecond, us).\r
+  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
 \r
   @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
   @retval EFI_TIMEOUT  The time out occurred.\r
@@ -515,16 +515,16 @@ XhcWaitOpRegBit (
   )\r
 {\r
   UINT32                  Index;\r
-  UINTN                   Loop;\r
+  UINT64                  Loop;\r
 \r
-  Loop   = (Timeout / XHC_POLL_DELAY) + 1;\r
+  Loop   = Timeout * XHC_1_MILLISECOND;\r
 \r
   for (Index = 0; Index < Loop; Index++) {\r
     if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r
       return EFI_SUCCESS;\r
     }\r
 \r
-    gBS->Stall (XHC_POLL_DELAY);\r
+    gBS->Stall (XHC_1_MICROSECOND);\r
   }\r
 \r
   return EFI_TIMEOUT;\r
@@ -656,7 +656,7 @@ XhcIsSysError (
   Reset the XHCI host controller.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in microsecond, us).\r
+  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
 \r
   @retval EFI_SUCCESS  The XHCI host controller is reset.\r
   @return Others       Failed to reset the XHCI before Timeout.\r
@@ -687,6 +687,12 @@ XhcResetHC (
   if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||\r
       ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {\r
     XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
+    //\r
+    // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.\r
+    // Otherwise there may have the timeout case happened.\r
+    // The below is a workaround to solve such problem.\r
+    //\r
+    gBS->Stall (XHC_1_MILLISECOND);\r
     Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
   }\r
 \r
@@ -698,7 +704,7 @@ XhcResetHC (
   Halt the XHCI host controller.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in microsecond, us).\r
+  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
 \r
   @return EFI_SUCCESS  The XHCI host controller is halt.\r
   @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
@@ -722,7 +728,7 @@ XhcHaltHC (
   Set the XHCI host controller to run.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in microsecond, us).\r
+  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
 \r
   @return EFI_SUCCESS  The XHCI host controller is running.\r
   @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r