MdeModulePkg/UfsPciHc: Avoid overriding return value in BindingStart

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
index 20a5510bfec9f714a3579ea221e50c9318b47682..b748c8d397395302c8b7058973e5b7e99574677a 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
@@ -2,7 +2,7 @@
 \r
   This file contains the register definition of XHCI host controller.\r
 \r
-Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -169,7 +169,7 @@ typedef union {
 #define XHC_PORTSC_RESET                   BIT4  // Port Reset\r
 #define XHC_PORTSC_PLS                     (BIT5|BIT6|BIT7|BIT8)     // Port Link State\r
 #define XHC_PORTSC_PP                      BIT9  // Port Power\r
-#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
+#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12)       // Port Speed\r
 #define XHC_PORTSC_LWS                     BIT16 // Port Link State Write Strobe\r
 #define XHC_PORTSC_CSC                     BIT17 // Connect Status Change\r
 #define XHC_PORTSC_PEC                     BIT18 // Port Enabled/Disabled Change\r
@@ -189,12 +189,23 @@ typedef union {
 #define XHC_HUB_PORTSC_PEC                 BIT17 // Hub's Port Enabled/Disabled Change\r
 #define XHC_HUB_PORTSC_OCC                 BIT19 // Hub's Over-Current Change\r
 #define XHC_HUB_PORTSC_PRC                 BIT20 // Hub's Port Reset Change\r
+#define XHC_HUB_PORTSC_BHRC                BIT21 // Hub's Port Warm Reset Change\r
 #define XHC_IMAN_IP                        BIT0  // Interrupt Pending\r
 #define XHC_IMAN_IE                        BIT1  // Interrupt Enable\r
 \r
 #define XHC_IMODI_MASK                     0x0000FFFF  // Interrupt Moderation Interval\r
 #define XHC_IMODC_MASK                     0xFFFF0000  // Interrupt Moderation Counter\r
 \r
+//\r
+//  Hub Class Feature Selector for Clear Port Feature Request\r
+//  It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
+//  For more details, Please refer to USB 3.0 Spec Table 10-7.\r
+//\r
+typedef enum {\r
+  Usb3PortBHPortReset          = 28,\r
+  Usb3PortBHPortResetChange    = 29\r
+} XHC_PORT_FEATURE;\r
+\r
 //\r
 // Structure to map the hardware port states to the\r
 // UEFI's port states.\r
@@ -204,6 +215,14 @@ typedef struct {
   UINT16                  UefiState;\r
 } USB_PORT_STATE_MAP;\r
 \r
+//\r
+// Structure to map the hardware port states to feature selector for clear port feature request.\r
+//\r
+typedef struct {\r
+  UINT32                  HwState;\r
+  UINT16                  Selector;\r
+} USB_CLEAR_PORT_MAP;\r
+\r
 /**\r
   Read 1-byte width XHCI capability register.\r
 \r
@@ -380,7 +399,7 @@ XhcClearOpRegBit (
   @param  Offset       The offset of the operational register.\r
   @param  Bit          The bit of the register to wait for.\r
   @param  WaitToSet    Wait the bit to set or clear.\r
-  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
+  @param  Timeout      The time to wait before abort (in microsecond, us).\r
 \r
   @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
   @retval EFI_TIMEOUT  The time out occurred.\r
@@ -502,7 +521,7 @@ XhcIsSysError (
   Reset the XHCI host controller.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
+  @param  Timeout      Time to wait before abort (in microsecond, us).\r
 \r
   @retval EFI_SUCCESS  The XHCI host controller is reset.\r
   @return Others       Failed to reset the XHCI before Timeout.\r
@@ -518,7 +537,7 @@ XhcResetHC (
   Halt the XHCI host controller.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
+  @param  Timeout      Time to wait before abort (in microsecond, us).\r
 \r
   @return EFI_SUCCESS  The XHCI host controller is halt.\r
   @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
@@ -534,7 +553,7 @@ XhcHaltHC (
   Set the XHCI host controller to run.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
+  @param  Timeout      Time to wait before abort (in microsecond, us).\r
 \r
   @return EFI_SUCCESS  The XHCI host controller is running.\r
   @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r