MdeModulePkg/Xhci: make all timeout values be consistent with comments.

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhcPeim.h

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
index 3b77f2aba7ab3e45f0d9030d3bb5f42c792777c3..ccf4dc26e551e8542a18b9feaf4e77b22197623f 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
@@ -1,7 +1,7 @@
 /** @file\r
 Private Header file for Usb Host Controller PEIM\r
 \r
-Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r
@@ -48,21 +48,20 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
 \r
 //\r
 // XHC reset timeout experience values.\r
-// The unit is microsecond, setting it as 1s.\r
+// The unit is millisecond, setting it as 1s.\r
 //\r
-#define XHC_RESET_TIMEOUT           (1 * XHC_1_SECOND)\r
-//\r
-// XHC delay experience value for polling operation.\r
-// The unit is microsecond, set it as 1ms.\r
-//\r
-#define XHC_POLL_DELAY              (1 * XHC_1_MILLISECOND)\r
+#define XHC_RESET_TIMEOUT           (1000)\r
 \r
 //\r
 // Wait for root port state stable.\r
 //\r
 #define XHC_ROOT_PORT_STATE_STABLE  (200 * XHC_1_MILLISECOND)\r
 \r
-#define XHC_GENERIC_TIMEOUT         (10 * XHC_1_MILLISECOND)\r
+//\r
+// XHC generic timeout experience values.\r
+// The unit is millisecond, setting it as 10s.\r
+//\r
+#define XHC_GENERIC_TIMEOUT         (10 * 1000)\r
 \r
 #define XHC_LOW_32BIT(Addr64)       ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
 #define XHC_HIGH_32BIT(Addr64)      ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r