MdeModulePkg/Xhci: make all timeout values be consistent with comments.

In the original code, there exists some mismatches between the real
waiting time and the corresponding timeout comments. For example, the
XHC_GENERIC_TIMEOUT comment says it's 10ms timeout value, but the real
code in fact waits 10s.

So the code is refined to be consistent in code logic and comments.

Note XHC_POLL_DELAY macro also be removed and the polling interval in
XhcWaitOpRegBit() is changed from 1ms to 1us to keep same code style
with other code. It has no real functionality impact.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18235 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
index 9927f7978338785471a910043e64271f213a05c9..7999151b3fdebb094b3addab446645749f7e9576 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h
@@ -2,7 +2,7 @@
 \r
   Provides some data structure definitions used by the XHCI host controller driver.\r
 \r
-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -47,24 +47,19 @@ typedef struct _USB_DEV_CONTEXT      USB_DEV_CONTEXT;
 //\r
 #define XHC_1_MICROSECOND            (1)\r
 //\r
-// Convert millisecond to microsecond.\r
+// The unit is microsecond, setting it as 1ms.\r
 //\r
 #define XHC_1_MILLISECOND            (1000)\r
 //\r
 // XHC generic timeout experience values.\r
-// The unit is microsecond, setting it as 10ms.\r
+// The unit is millisecond, setting it as 10s.\r
 //\r
 #define XHC_GENERIC_TIMEOUT          (10 * 1000)\r
 //\r
 // XHC reset timeout experience values.\r
-// The unit is microsecond, setting it as 1s.\r
+// The unit is millisecond, setting it as 1s.\r
 //\r
-#define XHC_RESET_TIMEOUT            (1000 * 1000)\r
-//\r
-// XHC delay experience value for polling operation.\r
-// The unit is microsecond, set it as 1ms.\r
-//\r
-#define XHC_POLL_DELAY               (1000)\r
+#define XHC_RESET_TIMEOUT            (1000)\r
 //\r
 // XHC async transfer timer interval, set by experience.\r
 // The unit is 100us, takes 1ms as interval.\r

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index a513dd958104ac0daa674c6054a3ba8f3035cb00..d0f22050addb07817c06e3b75bc378dea9d52c6d 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -2,7 +2,7 @@
 \r
   The XHCI register operation routines.\r
 \r
-Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -499,7 +499,7 @@ XhcClearOpRegBit (
   @param  Offset       The offset of the operation register.\r
   @param  Bit          The bit of the register to wait for.\r
   @param  WaitToSet    Wait the bit to set or clear.\r
-  @param  Timeout      The time to wait before abort (in microsecond, us).\r
+  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
 \r
   @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
   @retval EFI_TIMEOUT  The time out occurred.\r
@@ -515,16 +515,16 @@ XhcWaitOpRegBit (
   )\r
 {\r
   UINT32                  Index;\r
-  UINTN                   Loop;\r
+  UINT64                  Loop;\r
 \r
-  Loop   = (Timeout / XHC_POLL_DELAY) + 1;\r
+  Loop   = Timeout * XHC_1_MILLISECOND;\r
 \r
   for (Index = 0; Index < Loop; Index++) {\r
     if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r
       return EFI_SUCCESS;\r
     }\r
 \r
-    gBS->Stall (XHC_POLL_DELAY);\r
+    gBS->Stall (XHC_1_MICROSECOND);\r
   }\r
 \r
   return EFI_TIMEOUT;\r
@@ -656,7 +656,7 @@ XhcIsSysError (
   Reset the XHCI host controller.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in microsecond, us).\r
+  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
 \r
   @retval EFI_SUCCESS  The XHCI host controller is reset.\r
   @return Others       Failed to reset the XHCI before Timeout.\r
@@ -698,7 +698,7 @@ XhcResetHC (
   Halt the XHCI host controller.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in microsecond, us).\r
+  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
 \r
   @return EFI_SUCCESS  The XHCI host controller is halt.\r
   @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
@@ -722,7 +722,7 @@ XhcHaltHC (
   Set the XHCI host controller to run.\r
 \r
   @param  Xhc          The XHCI Instance.\r
-  @param  Timeout      Time to wait before abort (in microsecond, us).\r
+  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
 \r
   @return EFI_SUCCESS  The XHCI host controller is running.\r
   @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 1bdf1a4aa0f16b8d8da55f65a7189fa7b925dcf4..05cd616a034b102e815ee4783cb57d2a2b8e8a57 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -1215,7 +1215,7 @@ XhcExecTransfer (
 {\r
   EFI_STATUS              Status;\r
   UINTN                   Index;\r
-  UINTN                   Loop;\r
+  UINT64                  Loop;\r
   UINT8                   SlotId;\r
   UINT8                   Dci;\r
   BOOLEAN                 Finished;\r

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
index 72e86caeb0e98da60f20e28cf90673dfde124842..2f16b82d262028f27567f36e03ed1533f3c2c6c2 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
@@ -2,7 +2,7 @@
 PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid\r
 which is used to enable recovery function from USB Drivers.\r
 \r
-Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r
@@ -161,7 +161,7 @@ XhcPeiClearOpRegBit (
   @param  Offset        The offset of the operational register.\r
   @param  Bit           The bit mask of the register to wait for.\r
   @param  WaitToSet     Wait the bit to set or clear.\r
-  @param  Timeout       The time to wait before abort (in microsecond, us).\r
+  @param  Timeout       The time to wait before abort (in millisecond, ms).\r
 \r
   @retval EFI_SUCCESS   The bit successfully changed by host controller.\r
   @retval EFI_TIMEOUT   The time out occurred.\r
@@ -176,14 +176,14 @@ XhcPeiWaitOpRegBit (
   IN UINT32             Timeout\r
   )\r
 {\r
-  UINT32                Index;\r
+  UINT64                Index;\r
 \r
-  for (Index = 0; Index < Timeout / XHC_POLL_DELAY + 1; Index++) {\r
+  for (Index = 0; Index < Timeout * XHC_1_MILLISECOND; Index++) {\r
     if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r
       return EFI_SUCCESS;\r
     }\r
 \r
-    MicroSecondDelay (XHC_POLL_DELAY);\r
+    MicroSecondDelay (XHC_1_MICROSECOND);\r
   }\r
 \r
   return EFI_TIMEOUT;\r
@@ -381,7 +381,7 @@ XhcPeiIsSysError (
   Reset the host controller.\r
 \r
   @param  Xhc           The XHCI device.\r
-  @param  Timeout       Time to wait before abort (in microsecond, us).\r
+  @param  Timeout       Time to wait before abort (in millisecond, ms).\r
 \r
   @retval EFI_TIMEOUT   The transfer failed due to time out.\r
   @retval Others        Failed to reset the host.\r

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
index 3b77f2aba7ab3e45f0d9030d3bb5f42c792777c3..ccf4dc26e551e8542a18b9feaf4e77b22197623f 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
@@ -1,7 +1,7 @@
 /** @file\r
 Private Header file for Usb Host Controller PEIM\r
 \r
-Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r
@@ -48,21 +48,20 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
 \r
 //\r
 // XHC reset timeout experience values.\r
-// The unit is microsecond, setting it as 1s.\r
+// The unit is millisecond, setting it as 1s.\r
 //\r
-#define XHC_RESET_TIMEOUT           (1 * XHC_1_SECOND)\r
-//\r
-// XHC delay experience value for polling operation.\r
-// The unit is microsecond, set it as 1ms.\r
-//\r
-#define XHC_POLL_DELAY              (1 * XHC_1_MILLISECOND)\r
+#define XHC_RESET_TIMEOUT           (1000)\r
 \r
 //\r
 // Wait for root port state stable.\r
 //\r
 #define XHC_ROOT_PORT_STATE_STABLE  (200 * XHC_1_MILLISECOND)\r
 \r
-#define XHC_GENERIC_TIMEOUT         (10 * XHC_1_MILLISECOND)\r
+//\r
+// XHC generic timeout experience values.\r
+// The unit is millisecond, setting it as 10s.\r
+//\r
+#define XHC_GENERIC_TIMEOUT         (10 * 1000)\r
 \r
 #define XHC_LOW_32BIT(Addr64)       ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
 #define XHC_HIGH_32BIT(Addr64)      ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
index 0f35517ec62d846c349d51867fb5f8e6ef20a928..eedf3779be6116cb81a224b41a123e4427991858 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
@@ -736,7 +736,7 @@ XhcPeiExecTransfer (
 {\r
   EFI_STATUS    Status;\r
   UINTN         Index;\r
-  UINTN         Loop;\r
+  UINT64        Loop;\r
   UINT8         SlotId;\r
   UINT8         Dci;\r
   BOOLEAN       Finished;\r