\r
//\r
// Multiple APIC Description Table APIC structure types\r
-// All other values between 0x10 and 0x7F are reserved and\r
+// All other values between 0x18 and 0x7F are reserved and\r
// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\r
//\r
#define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC 0x00\r
#define EFI_ACPI_6_5_GICR 0x0E\r
#define EFI_ACPI_6_5_GIC_ITS 0x0F\r
#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP 0x10\r
+#define EFI_ACPI_6_5_CORE_PIC 0x11\r
+#define EFI_ACPI_6_5_LIO_PIC 0x12\r
+#define EFI_ACPI_6_5_HT_PIC 0x13\r
+#define EFI_ACPI_6_5_EIO_PIC 0x14\r
+#define EFI_ACPI_6_5_MSI_PIC 0x15\r
+#define EFI_ACPI_6_5_BIO_PIC 0x16\r
+#define EFI_ACPI_6_5_LPC_PIC 0x17\r
\r
//\r
// APIC Structure Definitions\r
#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000\r
#define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001\r
\r
+///\r
+/// Core Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT32 ProcessorId;\r
+ UINT32 CoreId;\r
+ UINT32 Flags;\r
+} EFI_ACPI_6_5_CORE_PIC_STRUCTURE;\r
+\r
+///\r
+/// Legacy I/O Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 Address;\r
+ UINT16 Size;\r
+ UINT8 Cascade[2];\r
+ UINT32 CascadeMap[2];\r
+} EFI_ACPI_6_5_LIO_PIC_STRUCTURE;\r
+\r
+///\r
+/// HyperTransport Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 Address;\r
+ UINT16 Size;\r
+ UINT8 Cascade[8];\r
+} EFI_ACPI_6_5_HT_PIC_STRUCTURE;\r
+\r
+///\r
+/// Extend I/O Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT8 Cascade;\r
+ UINT8 Node;\r
+ UINT64 NodeMap;\r
+} EFI_ACPI_6_5_EIO_PIC_STRUCTURE;\r
+\r
+///\r
+/// MSI Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 MsgAddress;\r
+ UINT32 Start;\r
+ UINT32 Count;\r
+} EFI_ACPI_6_5_MSI_PIC_STRUCTURE;\r
+\r
+///\r
+/// Bridge I/O Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 Address;\r
+ UINT16 Size;\r
+ UINT16 Id;\r
+ UINT16 GsiBase;\r
+} EFI_ACPI_6_5_BIO_PIC_STRUCTURE;\r
+\r
+///\r
+/// Low Pin Count Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 Address;\r
+ UINT16 Size;\r
+ UINT8 Cascade;\r
+} EFI_ACPI_6_5_LPC_PIC_STRUCTURE;\r
+\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r