MdePkg: Added serveral tables to MATD used by LoongArch64

Add CORE_PIC, LIO_PIC, HT_PIC, EIO_PIC, MSI_PIC, BIO_PIC and LPC_PIC
tables for LoongArch64 as defined in ACPI SPEC 6.5.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4306

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

diff --git a/MdePkg/Include/IndustryStandard/Acpi65.h b/MdePkg/Include/IndustryStandard/Acpi65.h
index fdca5316a9136d7f3fec21c3ccd7b543b6520395..1e41ae9a27dbad64ae1311f722198aba1287aa6f 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Acpi65.h
+++ b/MdePkg/Include/IndustryStandard/Acpi65.h
@@ -303,7 +303,7 @@ typedef struct {
 \r
 //\r
 // Multiple APIC Description Table APIC structure types\r
-// All other values between 0x10 and 0x7F are reserved and\r
+// All other values between 0x18 and 0x7F are reserved and\r
 // will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.\r
 //\r
 #define EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC           0x00\r
@@ -323,6 +323,13 @@ typedef struct {
 #define EFI_ACPI_6_5_GICR                           0x0E\r
 #define EFI_ACPI_6_5_GIC_ITS                        0x0F\r
 #define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP          0x10\r
+#define EFI_ACPI_6_5_CORE_PIC                       0x11\r
+#define EFI_ACPI_6_5_LIO_PIC                        0x12\r
+#define EFI_ACPI_6_5_HT_PIC                         0x13\r
+#define EFI_ACPI_6_5_EIO_PIC                        0x14\r
+#define EFI_ACPI_6_5_MSI_PIC                        0x15\r
+#define EFI_ACPI_6_5_BIO_PIC                        0x16\r
+#define EFI_ACPI_6_5_LPC_PIC                        0x17\r
 \r
 //\r
 // APIC Structure Definitions\r
@@ -617,6 +624,92 @@ typedef struct {
 #define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP    0x0000\r
 #define EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP  0x0001\r
 \r
+///\r
+/// Core Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+  UINT8     Type;\r
+  UINT8     Length;\r
+  UINT8     Version;\r
+  UINT32    ProcessorId;\r
+  UINT32    CoreId;\r
+  UINT32    Flags;\r
+} EFI_ACPI_6_5_CORE_PIC_STRUCTURE;\r
+\r
+///\r
+/// Legacy I/O Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+  UINT8     Type;\r
+  UINT8     Length;\r
+  UINT8     Version;\r
+  UINT64    Address;\r
+  UINT16    Size;\r
+  UINT8     Cascade[2];\r
+  UINT32    CascadeMap[2];\r
+} EFI_ACPI_6_5_LIO_PIC_STRUCTURE;\r
+\r
+///\r
+/// HyperTransport Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+  UINT8     Type;\r
+  UINT8     Length;\r
+  UINT8     Version;\r
+  UINT64    Address;\r
+  UINT16    Size;\r
+  UINT8     Cascade[8];\r
+} EFI_ACPI_6_5_HT_PIC_STRUCTURE;\r
+\r
+///\r
+/// Extend I/O Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+  UINT8     Type;\r
+  UINT8     Length;\r
+  UINT8     Version;\r
+  UINT8     Cascade;\r
+  UINT8     Node;\r
+  UINT64    NodeMap;\r
+} EFI_ACPI_6_5_EIO_PIC_STRUCTURE;\r
+\r
+///\r
+/// MSI Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+  UINT8     Type;\r
+  UINT8     Length;\r
+  UINT8     Version;\r
+  UINT64    MsgAddress;\r
+  UINT32    Start;\r
+  UINT32    Count;\r
+} EFI_ACPI_6_5_MSI_PIC_STRUCTURE;\r
+\r
+///\r
+/// Bridge I/O Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+  UINT8     Type;\r
+  UINT8     Length;\r
+  UINT8     Version;\r
+  UINT64    Address;\r
+  UINT16    Size;\r
+  UINT16    Id;\r
+  UINT16    GsiBase;\r
+} EFI_ACPI_6_5_BIO_PIC_STRUCTURE;\r
+\r
+///\r
+/// Low Pin Count Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+  UINT8     Type;\r
+  UINT8     Length;\r
+  UINT8     Version;\r
+  UINT64    Address;\r
+  UINT16    Size;\r
+  UINT8     Cascade;\r
+} EFI_ACPI_6_5_LPC_PIC_STRUCTURE;\r
+\r
 ///\r
 /// Smart Battery Description Table (SBST)\r
 ///\r