+///\r
+/// Core Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT32 ProcessorId;\r
+ UINT32 CoreId;\r
+ UINT32 Flags;\r
+} EFI_ACPI_6_5_CORE_PIC_STRUCTURE;\r
+\r
+///\r
+/// Legacy I/O Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 Address;\r
+ UINT16 Size;\r
+ UINT8 Cascade[2];\r
+ UINT32 CascadeMap[2];\r
+} EFI_ACPI_6_5_LIO_PIC_STRUCTURE;\r
+\r
+///\r
+/// HyperTransport Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 Address;\r
+ UINT16 Size;\r
+ UINT8 Cascade[8];\r
+} EFI_ACPI_6_5_HT_PIC_STRUCTURE;\r
+\r
+///\r
+/// Extend I/O Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT8 Cascade;\r
+ UINT8 Node;\r
+ UINT64 NodeMap;\r
+} EFI_ACPI_6_5_EIO_PIC_STRUCTURE;\r
+\r
+///\r
+/// MSI Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 MsgAddress;\r
+ UINT32 Start;\r
+ UINT32 Count;\r
+} EFI_ACPI_6_5_MSI_PIC_STRUCTURE;\r
+\r
+///\r
+/// Bridge I/O Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 Address;\r
+ UINT16 Size;\r
+ UINT16 Id;\r
+ UINT16 GsiBase;\r
+} EFI_ACPI_6_5_BIO_PIC_STRUCTURE;\r
+\r
+///\r
+/// Low Pin Count Programmable Interrupt Controller\r
+///\r
+typedef struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Version;\r
+ UINT64 Address;\r
+ UINT16 Size;\r
+ UINT8 Cascade;\r
+} EFI_ACPI_6_5_LPC_PIC_STRUCTURE;\r
+\r