#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
+#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\r
\r
///\r
/// Capabilities List Header\r
UINT8 NextItemPtr;\r
} EFI_PCI_CAPABILITY_HDR;\r
\r
-///\r
-/// Power Management Register Block Definition \r
-/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
-///\r
-typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 PMC;\r
- UINT16 PMCSR;\r
- UINT8 BridgeExtention;\r
- UINT8 Data;\r
-} EFI_PCI_CAPABILITY_PMI;\r
-\r
///\r
/// PMC - Power Management Capabilities\r
/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r
typedef union {\r
struct {\r
UINT16 PowerState : 2;\r
- UINT16 Reserved : 6;\r
+ UINT16 ReservedForPciExpress : 1;\r
+ UINT16 NoSoftReset : 1;\r
+ UINT16 Reserved : 4;\r
UINT16 PmeEnable : 1;\r
UINT16 DataSelect : 4;\r
UINT16 DataScale : 2;\r
UINT16 Data;\r
} EFI_PCI_PMCSR;\r
\r
+#define PCI_POWER_STATE_D0 0\r
+#define PCI_POWER_STATE_D1 1\r
+#define PCI_POWER_STATE_D2 2\r
+#define PCI_POWER_STATE_D3_HOT 3\r
+\r
+///\r
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
+/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 6;\r
+ UINT8 B2B3 : 1;\r
+ UINT8 BusPowerClockControl : 1;\r
+ } Bits;\r
+ UINT8 Uint8;\r
+} EFI_PCI_PMCSR_BSE;\r
+\r
+///\r
+/// Power Management Register Block Definition\r
+/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
+///\r
+typedef struct {\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ EFI_PCI_PMC PMC;\r
+ EFI_PCI_PMCSR PMCSR;\r
+ EFI_PCI_PMCSR_BSE BridgeExtention;\r
+ UINT8 Data;\r
+} EFI_PCI_CAPABILITY_PMI;\r
+\r
///\r
/// A.G.P Capability\r
/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r