MdePkg/IndustryStandard: Fix various typos

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pci22.h

diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 5fd054c4cfbe975e4820044bd2a1dabef12951df..81a854f69577a21ab7083164892a4b6bd838b326 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -5,7 +5,7 @@
     PCI Local Bus Specification, 2.2\r
     PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
     PC Card Standard, 8.0\r
-    PCI Power Management Interface Specifiction, Revision 1.2\r
+    PCI Power Management Interface Specification, Revision 1.2\r
 \r
   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
   Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r
@@ -111,11 +111,11 @@ typedef union {
 } PCI_TYPE_GENERIC;\r
 \r
 ///\r
-/// CardBus Conroller Configuration Space,\r
+/// CardBus Controller Configuration Space,\r
 /// Section 4.5.1, PC Card Standard. 8.0\r
 ///\r
 typedef struct {\r
-  UINT32  CardBusSocketReg;     ///< Cardus Socket/ExCA Base\r
+  UINT32  CardBusSocketReg;     ///< Cardbus Socket/ExCA Base\r
   UINT8   Cap_Ptr;\r
   UINT8   Reserved;\r
   UINT16  SecondaryStatus;      ///< Secondary Status\r
@@ -222,7 +222,7 @@ typedef struct {
 #define     PCI_IF_8259_PIC               0x00\r
 #define     PCI_IF_ISA_PIC                0x01\r
 #define     PCI_IF_EISA_PIC               0x02\r
-#define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.\r
+#define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.\r
 #define     PCI_IF_APIC_CONTROLLER2       0x20\r
 #define   PCI_SUBCLASS_DMA              0x01\r
 #define     PCI_IF_8237_DMA               0x00\r
@@ -509,7 +509,7 @@ typedef struct {
 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
 \r
 ///\r
-/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,\r
+/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,\r
 ///\r
 #define PCI_BRIDGE_ROMBAR             0x38\r
 \r
@@ -642,7 +642,7 @@ typedef struct {
 \r
 ///\r
 /// PMC - Power Management Capabilities\r
-/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2\r
+/// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2\r
 ///\r
 typedef union {\r
   struct {\r
@@ -662,7 +662,7 @@ typedef union {
 \r
 ///\r
 /// PMCSR - Power Management Control/Status\r
-/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2\r
+/// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2\r
 ///\r
 typedef union {\r
   struct {\r
@@ -685,7 +685,7 @@ typedef union {
 \r
 ///\r
 /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
-/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2\r
+/// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2\r
 ///\r
 typedef union {\r
   struct {\r
@@ -698,7 +698,7 @@ typedef union {
 \r
 ///\r
 /// Power Management Register Block Definition\r
-/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2\r
+/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r
@@ -732,7 +732,7 @@ typedef struct {
 \r
 ///\r
 /// Slot Numbering Capabilities Register\r
-/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2\r
+/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
 ///\r
 typedef struct {\r
   EFI_PCI_CAPABILITY_HDR  Hdr;\r