--- /dev/null
+/** @file\r
+ This file contains definitions for SPD LPDDR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Revision Reference:\r
+ - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2\r
+ http://www.jedec.org/standards-documents/docs/spd412m-2\r
+**/\r
+\r
+#ifndef _SDRAM_SPD_LPDDR_H_\r
+#define _SDRAM_SPD_LPDDR_H_\r
+\r
+#pragma pack (push, 1)\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 BytesUsed : 4; ///< Bits 3:0\r
+ UINT8 BytesTotal : 3; ///< Bits 6:4\r
+ UINT8 CrcCoverage : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Minor : 4; ///< Bits 3:0\r
+ UINT8 Major : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_REVISION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Type : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ModuleType : 4; ///< Bits 3:0\r
+ UINT8 HybridMedia : 3; ///< Bits 6:4\r
+ UINT8 Hybrid : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Density : 4; ///< Bits 3:0\r
+ UINT8 BankAddress : 2; ///< Bits 5:4\r
+ UINT8 BankGroup : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ColumnAddress : 3; ///< Bits 2:0\r
+ UINT8 RowAddress : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_ADDRESSING_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 ChannelsPerDie : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramPackageType : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 5; ///< Bits 4:0\r
+ UINT8 SoftPPR : 1; ///< Bits 5:5\r
+ UINT8 PostPackageRepair : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r
+ UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r
+ UINT8 OperationAt1_10 : 1; ///< Bits 2:2\r
+ UINT8 EndurantAt1_10 : 1; ///< Bits 3:3\r
+ UINT8 OperationAtTBD2V : 1; ///< Bits 4:4\r
+ UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
+ UINT8 RankCount : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_ORGANIZATION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
+ UINT8 NumberofChannels : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Reserved : 7; ///< Bits 6:0\r
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ChipSelectLoading : 3; ///< Bits 2:0\r
+ UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3\r
+ UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_SIGNAL_LOADING_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Fine : 2; ///< Bits 1:0\r
+ UINT8 Medium : 2; ///< Bits 3:2\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TIMEBASE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tCKmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TCK_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tCKmax : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TCK_MAX_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 Cl3 : 1; ///< Bits 0:0\r
+ UINT32 Cl6 : 1; ///< Bits 1:1\r
+ UINT32 Cl8 : 1; ///< Bits 2:2\r
+ UINT32 Cl9 : 1; ///< Bits 3:3\r
+ UINT32 Cl10 : 1; ///< Bits 4:4\r
+ UINT32 Cl11 : 1; ///< Bits 5:5\r
+ UINT32 Cl12 : 1; ///< Bits 6:6\r
+ UINT32 Cl14 : 1; ///< Bits 7:7\r
+ UINT32 Cl16 : 1; ///< Bits 8:8\r
+ UINT32 Reserved0 : 1; ///< Bits 9:9\r
+ UINT32 Cl20 : 1; ///< Bits 10:10\r
+ UINT32 Cl22 : 1; ///< Bits 11:11\r
+ UINT32 Cl24 : 1; ///< Bits 12:12\r
+ UINT32 Reserved1 : 1; ///< Bits 13:13\r
+ UINT32 Cl28 : 1; ///< Bits 14:14\r
+ UINT32 Reserved2 : 1; ///< Bits 15:15\r
+ UINT32 Cl32 : 1; ///< Bits 16:16\r
+ UINT32 Reserved3 : 1; ///< Bits 17:17\r
+ UINT32 Cl36 : 1; ///< Bits 18:18\r
+ UINT32 Reserved4 : 1; ///< Bits 19:19\r
+ UINT32 Cl40 : 1; ///< Bits 20:20\r
+ UINT32 Reserved5 : 11; ///< Bits 31:21\r
+ } Bits;\r
+ UINT32 Data;\r
+ UINT16 Data16[2];\r
+ UINT8 Data8[4];\r
+} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tAAmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TAA_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 ReadLatencyMode : 2; ///< Bits 1:0\r
+ UINT8 WriteLatencySet : 2; ///< Bits 3:2\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRCDmin : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TRCD_MIN_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRPab : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TRP_AB_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 tRPpb : 8; ///< Bits 7:0\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_TRP_PB_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 tRFCab : 16; ///< Bits 15:0\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD_LPDDR_TRFC_AB_MTB_STRUCT;\r
+\r
+typedef union {\r
+struct {\r
+ UINT16 tRFCpb : 16; ///< Bits 15:0\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD_LPDDR_TRFC_PB_MTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r
+ UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r
+ UINT8 PackageRankMap : 2; ///< Bits 7:6\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRPpbFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TRP_PB_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRPabFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TRP_AB_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tRCDminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TRCD_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tAAminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TAA_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tCKmaxFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TCK_MAX_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ INT8 tCKminFine : 8; ///< Bits 7:0\r
+ } Bits;\r
+ INT8 Data;\r
+} SPD_LPDDR_TCK_MIN_FTB_STRUCT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
+} SPD_LPDDR_MANUFACTURER_ID_CODE;\r
+\r
+typedef struct {\r
+ UINT8 Location; ///< Module Manufacturing Location\r
+} SPD_LPDDR_MANUFACTURING_LOCATION;\r
+\r
+typedef struct {\r
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
+} SPD_LPDDR_MANUFACTURING_DATE;\r
+\r
+typedef union {\r
+ UINT32 Data;\r
+ UINT16 SerialNumber16[2];\r
+ UINT8 SerialNumber8[4];\r
+} SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER;\r
+\r
+typedef struct {\r
+ SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
+ SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
+ SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
+ SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
+} SPD_LPDDR_UNIQUE_MODULE_ID;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 RawCardExtension : 3; ///< Bits 7:5\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_MODULE_NOMINAL_HEIGHT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
+ } Bits;\r
+ UINT8 Data;\r
+} SPD_LPDDR_REFERENCE_RAW_CARD;\r
+\r
+typedef union {\r
+ UINT16 Crc[1];\r
+ UINT8 Data8[2];\r
+} SPD_LPDDR_CYCLIC_REDUNDANCY_CODE;\r
+\r
+typedef struct {\r
+ SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
+ SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
+ SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
+ SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
+ SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
+ SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
+ SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type\r
+ SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r
+ SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r
+ SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r
+ UINT8 Reserved0; ///< 10 Reserved\r
+ SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r
+ SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r
+ SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r
+ SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r
+ SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r
+ SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading\r
+ SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r
+ SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r
+ SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r
+ SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r
+ SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options\r
+ SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks\r
+ SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank\r
+ SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks\r
+ SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank\r
+ UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved\r
+ SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r
+ UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved\r
+ SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank\r
+ SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks\r
+ SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
+ SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)\r
+ SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
+} SPD_LPDDR_BASE_SECTION;\r
+\r
+typedef struct {\r
+ SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
+ SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
+ SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
+ UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved\r
+ SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+} SPD_LPDDR_MODULE_LPDIMM;\r
+\r
+typedef struct {\r
+ SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types\r
+} SPD_LPDDR_MODULE_SPECIFIC;\r
+\r
+typedef struct {\r
+ UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r
+} SPD_LPDDR_MODULE_PART_NUMBER;\r
+\r
+typedef struct {\r
+ UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r
+} SPD_LPDDR_MANUFACTURER_SPECIFIC;\r
+\r
+typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code\r
+typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping\r
+\r
+typedef struct {\r
+ SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r
+ SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r
+ SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r
+ SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r
+ SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r
+ SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r
+ UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved\r
+} SPD_LPDDR_MANUFACTURING_DATA;\r
+\r
+typedef struct {\r
+ UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable\r
+} SPD_LPDDR_END_USER_SECTION;\r
+\r
+///\r
+/// LPDDR Serial Presence Detect structure\r
+///\r
+typedef struct {\r
+ SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r
+ SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r
+ UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters\r
+ SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r
+ SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r
+} SPD_LPDDR;\r
+\r
+#pragma pack (pop)\r
+#endif\r
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