#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E\r
#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F\r
\r
+#define IA32_GDT_TYPE_TSS 0x9\r
+#define IA32_GDT_ALIGNMENT 8\r
\r
#if defined (MDE_CPU_IA32)\r
///\r
UINT64 Uint64;\r
} IA32_IDT_GATE_DESCRIPTOR;\r
\r
+#pragma pack (1)\r
+//\r
+// IA32 Task-State Segment Definition\r
+//\r
+typedef struct {\r
+ UINT16 PreviousTaskLink;\r
+ UINT16 Reserved_2;\r
+ UINT32 ESP0;\r
+ UINT16 SS0;\r
+ UINT16 Reserved_10;\r
+ UINT32 ESP1;\r
+ UINT16 SS1;\r
+ UINT16 Reserved_18;\r
+ UINT32 ESP2;\r
+ UINT16 SS2;\r
+ UINT16 Reserved_26;\r
+ UINT32 CR3;\r
+ UINT32 EIP;\r
+ UINT32 EFLAGS;\r
+ UINT32 EAX;\r
+ UINT32 ECX;\r
+ UINT32 EDX;\r
+ UINT32 EBX;\r
+ UINT32 ESP;\r
+ UINT32 EBP;\r
+ UINT32 ESI;\r
+ UINT32 EDI;\r
+ UINT16 ES;\r
+ UINT16 Reserved_74;\r
+ UINT16 CS;\r
+ UINT16 Reserved_78;\r
+ UINT16 SS;\r
+ UINT16 Reserved_82;\r
+ UINT16 DS;\r
+ UINT16 Reserved_86;\r
+ UINT16 FS;\r
+ UINT16 Reserved_90;\r
+ UINT16 GS;\r
+ UINT16 Reserved_94;\r
+ UINT16 LDTSegmentSelector;\r
+ UINT16 Reserved_98;\r
+ UINT16 T;\r
+ UINT16 IOMapBaseAddress;\r
+} IA32_TASK_STATE_SEGMENT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 LimitLow:16; ///< Segment Limit 15..00\r
+ UINT32 BaseLow:16; ///< Base Address 15..00\r
+ UINT32 BaseMid:8; ///< Base Address 23..16\r
+ UINT32 Type:4; ///< Type (1 0 B 1)\r
+ UINT32 Reserved_43:1; ///< 0\r
+ UINT32 DPL:2; ///< Descriptor Privilege Level\r
+ UINT32 P:1; ///< Segment Present\r
+ UINT32 LimitHigh:4; ///< Segment Limit 19..16\r
+ UINT32 AVL:1; ///< Available for use by system software\r
+ UINT32 Reserved_52:2; ///< 0 0\r
+ UINT32 G:1; ///< Granularity\r
+ UINT32 BaseHigh:8; ///< Base Address 31..24\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} IA32_TSS_DESCRIPTOR;\r
+#pragma pack ()\r
+\r
#endif\r
\r
#if defined (MDE_CPU_X64)\r
} Uint128; \r
} IA32_IDT_GATE_DESCRIPTOR;\r
\r
+#pragma pack (1)\r
+//\r
+// IA32 Task-State Segment Definition\r
+//\r
+typedef struct {\r
+ UINT32 Reserved_0;\r
+ UINT64 RSP0;\r
+ UINT64 RSP1;\r
+ UINT64 RSP2;\r
+ UINT64 Reserved_28;\r
+ UINT64 IST[7];\r
+ UINT64 Reserved_92;\r
+ UINT16 Reserved_100;\r
+ UINT16 IOMapBaseAddress;\r
+} IA32_TASK_STATE_SEGMENT;\r
+\r
+typedef union {\r
+ struct {\r
+ UINT32 LimitLow:16; ///< Segment Limit 15..00\r
+ UINT32 BaseLow:16; ///< Base Address 15..00\r
+ UINT32 BaseMidl:8; ///< Base Address 23..16\r
+ UINT32 Type:4; ///< Type (1 0 B 1)\r
+ UINT32 Reserved_43:1; ///< 0\r
+ UINT32 DPL:2; ///< Descriptor Privilege Level\r
+ UINT32 P:1; ///< Segment Present\r
+ UINT32 LimitHigh:4; ///< Segment Limit 19..16\r
+ UINT32 AVL:1; ///< Available for use by system software\r
+ UINT32 Reserved_52:2; ///< 0 0\r
+ UINT32 G:1; ///< Granularity\r
+ UINT32 BaseMidh:8; ///< Base Address 31..24\r
+ UINT32 BaseHigh:32; ///< Base Address 63..32\r
+ UINT32 Reserved_96:32; ///< Reserved\r
+ } Bits;\r
+ struct {\r
+ UINT64 Uint64;\r
+ UINT64 Uint64_1;\r
+ } Uint128;\r
+} IA32_TSS_DESCRIPTOR;\r
+#pragma pack ()\r
+\r
#endif\r
\r
///\r
OUT UINT64 *Rand\r
);\r
\r
+/**\r
+ Load given selector into TR register\r
+\r
+ @param[in] Selector Task segment selector\r
+**/\r
+VOID\r
+EFIAPI\r
+AsmWriteTr (\r
+ IN UINT16 Selector\r
+ );\r
+\r
#endif\r
#endif\r
\r