/** @file\r
StatusCode related definitions in PI.\r
\r
- Copyright (c) 2009, Intel Corporation \r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials are licensed and made available under \r
+the terms and conditions of the BSD License that accompanies this distribution. \r
+The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php. \r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
\r
@par Revision Reference:\r
- These status codes are defined in UEFI Platform Initialization Specification 1.2 \r
- Volume 3: Shared Architectural Elements\r
+ These status codes are defined in UEFI Platform Initialization Specification 1.2, \r
+ Volume 3: Shared Architectural Elements.\r
\r
**/\r
\r
#define __PI_STATUS_CODE_H__\r
\r
//\r
-// Required for IA32 and IPF defines for CPU exception types\r
+// Required for IA32, X64, IPF, ARM and EBC defines for CPU exception types\r
//\r
#include <Protocol/DebugSupport.h>\r
\r
///\r
-/// Status Code Type Definition\r
+/// Status Code Type Definition.\r
///\r
typedef UINT32 EFI_STATUS_CODE_TYPE;\r
\r
///\r
-/// A Status Code Type is made up of the code type and severity\r
+/// A Status Code Type is made up of the code type and severity.\r
/// All values masked by EFI_STATUS_CODE_RESERVED_MASK are\r
/// reserved for use by this specification.\r
///\r
///@}\r
\r
///\r
-/// Definition of code types, all other values masked by\r
+/// Definition of code types. All other values masked by\r
/// EFI_STATUS_CODE_TYPE_MASK are reserved for use by\r
/// this specification.\r
///\r
/// EFI_STATUS_CODE_SEVERITY_MASK are reserved for use by\r
/// this specification.\r
/// Uncontained errors are major errors that could not contained\r
-/// to the specific component that is reporting the error\r
+/// to the specific component that is reporting the error.\r
/// For example, if a memory error was not detected early enough,\r
/// the bad data could be consumed by other drivers.\r
///\r
///@}\r
\r
///\r
-/// Status Code Value Definition\r
+/// Status Code Value Definition.\r
///\r
typedef UINT32 EFI_STATUS_CODE_VALUE;\r
\r
} EFI_STATUS_CODE_DATA;\r
\r
///\r
-/// General partitioning scheme for Progress and Error Codes are\r
-/// - 0x0000-0x0FFF Shared by all sub-classes in a given class\r
-/// - 0x1000-0x7FFF Subclass Specific\r
-/// - 0x8000-0xFFFF OEM specific\r
+/// General partitioning scheme for Progress and Error Codes are:\r
+/// - 0x0000-0x0FFF Shared by all sub-classes in a given class.\r
+/// - 0x1000-0x7FFF Subclass Specific.\r
+/// - 0x8000-0xFFFF OEM specific.\r
///@{\r
#define EFI_SUBCLASS_SPECIFIC 0x1000\r
#define EFI_OEM_SPECIFIC 0x8000\r
///@}\r
\r
///\r
-/// Debug Code definitions for all classes and subclass\r
+/// Debug Code definitions for all classes and subclass.\r
/// Only one debug code is defined at this point and should\r
-/// be used for anything that gets sent to debug stream.\r
+/// be used for anything that is sent to the debug stream.\r
///\r
///@{\r
#define EFI_DC_UNSPECIFIED 0x0\r
///@}\r
\r
///\r
-/// Class definitions\r
+/// Class definitions.\r
/// Values of 4-127 are reserved for future use by this specification.\r
/// Values in the range 127-255 are reserved for OEM use.\r
///\r
//\r
\r
///\r
-/// South Bridge initialization prior to memory detection\r
+/// South Bridge initialization prior to memory detection.\r
///\r
#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000)\r
\r
///\r
-/// North Bridge initialization prior to memory detection\r
+/// North Bridge initialization prior to memory detection.\r
///\r
#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001)\r
\r
///\r
-/// South Bridge initialization after memory detection\r
+/// South Bridge initialization after memory detection.\r
///\r
#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002)\r
\r
///\r
-/// North Bridge initialization after memory detection\r
+/// North Bridge initialization after memory detection.\r
///\r
#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003)\r
\r
///\r
-/// PCI Host Bridge DXE initialization\r
+/// PCI Host Bridge DXE initialization.\r
///\r
#define EFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004)\r
\r
///\r
-/// North Bridge DXE initialization\r
+/// North Bridge DXE initialization.\r
///\r
#define EFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005)\r
\r
///\r
-/// North Bridge specific SMM initialization in DXE\r
+/// North Bridge specific SMM initialization in DXE.\r
///\r
#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006)\r
\r
///\r
-/// Initialization of the South Bridge specific UEFI Runtime Services\r
+/// Initialization of the South Bridge specific UEFI Runtime Services.\r
///\r
#define EFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007)\r
\r
#define EFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008)\r
\r
///\r
-/// South Bridge specific SMM initialization in DXE\r
+/// South Bridge specific SMM initialization in DXE.\r
///\r
#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009)\r
\r
///\r
-/// Initialization of the South Bridge devices\r
+/// Initialization of the South Bridge devices.\r
///\r
#define EFI_CHIPSET_PC_DXE_SB_DEVICES_INIT (EFI_SUBCLASS_SPECIFIC|0x0000000a)\r
\r
/// IO Bus Class PCI Subclass Progress Code definitions.\r
///\r
///@{\r
-#define EFI_IOB_PCI_PC_BUS_ENUM (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_IOB_PCI_PC_RES_ALLOC (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_IOB_PCI_PC_HPC_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_IOB_PCI_BUS_ENUM (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_IOB_PCI_RES_ALLOC (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_IOB_PCI_HPC_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
///@}\r
\r
//\r
//\r
// IO Bus Class ATA/ATAPI Subclass Progress Code definitions.\r
//\r
-\r
+#define EFI_IOB_ATA_BUS_SMART_ENABLE (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_IOB_ATA_BUS_SMART_DISABLE (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
//\r
// IO Bus Class FC Subclass Progress Code definitions.\r
//\r
//\r
// IO Bus Class ATA/ATAPI Subclass Error Code definitions.\r
//\r
+#define EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_IOB_ATA_BUS_SMART_DISABLED (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
\r
//\r
// IO Bus Class FC Subclass Error Code definitions.\r
#define EFI_SOFTWARE_EFI_BOOT_SERVICE (EFI_SOFTWARE | 0x00100000)\r
#define EFI_SOFTWARE_EFI_RUNTIME_SERVICE (EFI_SOFTWARE | 0x00110000)\r
#define EFI_SOFTWARE_EFI_DXE_SERVICE (EFI_SOFTWARE | 0x00120000)\r
+#define EFI_SOFTWARE_X64_EXCEPTION (EFI_SOFTWARE | 0x00130000)\r
+#define EFI_SOFTWARE_ARM_EXCEPTION (EFI_SOFTWARE | 0x00140000)\r
+\r
///@}\r
\r
///\r
/// Software Class PEI Module Subclass Progress Code definitions.\r
///\r
///@{\r
-#define EFI_SW_PEIM_PC_RECOVERY_BEGIN (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_SW_PEIM_PC_CAPSULE_LOAD (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_SW_PEIM_PC_CAPSULE_START (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
-#define EFI_SW_PEIM_PC_RECOVERY_USER (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
-#define EFI_SW_PEIM_PC_RECOVERY_AUTO (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_SW_PEI_PC_RECOVERY_BEGIN (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_PEI_PC_CAPSULE_LOAD (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_SW_PEI_PC_CAPSULE_START (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_SW_PEI_PC_RECOVERY_USER (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_SW_PEI_PC_RECOVERY_AUTO (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_SW_PEI_PC_S3_BOOT_SCRIPT (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+#define EFI_SW_PEI_PC_OS_WAKE (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
///@}\r
\r
///\r
#define EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
#define EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVICES_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
#define EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_SW_DXE_BS_PC_ATTEMPT_BOOT_ORDER_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
///@}\r
\r
//\r
#define EFI_SW_RT_PC_RETURN_TO_LAST (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
///@}\r
\r
+//\r
+// Software Class X64 Exception Subclass Progress Code definitions.\r
+//\r
+\r
+//\r
+// Software Class ARM Exception Subclass Progress Code definitions.\r
+//\r
+\r
//\r
// Software Class EBC Exception Subclass Progress Code definitions.\r
//\r
/// Software Class PEI Module Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_SW_PEIM_EC_INVALID_CAPSULE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_SW_PEI_EC_NO_RECOVERY_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_PEI_EC_INVALID_CAPSULE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
#define EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
#define EFI_SW_PEI_EC_S3_BOOT_SCRIPT_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
#define EFI_SW_PEI_EC_S3_OS_WAKE_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
// Software Class EFI Runtime Service Subclass Error Code definitions.\r
//\r
\r
-//\r
-// Software Class EFI DXE Service Subclass Error Code definitions.\r
-//\r
+///\r
+/// Software Class EFI DXE Service Subclass Error Code definitions.\r
+///\r
+///@{\r
+#define EFI_SW_DXE_BS_PC_BEGIN_CONNECTING_DRIVERS (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+#define EFI_SW_DXE_BS_PC_VERIFYING_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
+///@}\r
+\r
+///\r
+/// Software Class DXE RT Driver Subclass Progress Code definitions.\r
+///\r
+///@{\r
+#define EFI_SW_DXE_RT_PC_S0 (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_DXE_RT_PC_S1 (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_SW_DXE_RT_PC_S2 (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_SW_DXE_RT_PC_S3 (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_SW_DXE_RT_PC_S4 (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_SW_DXE_RT_PC_S5 (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+///@}\r
+\r
+///\r
+/// Software Class X64 Exception Subclass Error Code definitions.\r
+/// These exceptions are derived from the debug protocol\r
+/// definitions in the EFI specification.\r
+///\r
+///@{\r
+#define EFI_SW_EC_X64_DIVIDE_ERROR EXCEPT_X64_DIVIDE_ERROR\r
+#define EFI_SW_EC_X64_DEBUG EXCEPT_X64_DEBUG\r
+#define EFI_SW_EC_X64_NMI EXCEPT_X64_NMI\r
+#define EFI_SW_EC_X64_BREAKPOINT EXCEPT_X64_BREAKPOINT\r
+#define EFI_SW_EC_X64_OVERFLOW EXCEPT_X64_OVERFLOW\r
+#define EFI_SW_EC_X64_BOUND EXCEPT_X64_BOUND\r
+#define EFI_SW_EC_X64_INVALID_OPCODE EXCEPT_X64_INVALID_OPCODE\r
+#define EFI_SW_EC_X64_DOUBLE_FAULT EXCEPT_X64_DOUBLE_FAULT\r
+#define EFI_SW_EC_X64_INVALID_TSS EXCEPT_X64_INVALID_TSS\r
+#define EFI_SW_EC_X64_SEG_NOT_PRESENT EXCEPT_X64_SEG_NOT_PRESENT\r
+#define EFI_SW_EC_X64_STACK_FAULT EXCEPT_X64_STACK_FAULT\r
+#define EFI_SW_EC_X64_GP_FAULT EXCEPT_X64_GP_FAULT\r
+#define EFI_SW_EC_X64_PAGE_FAULT EXCEPT_X64_PAGE_FAULT\r
+#define EFI_SW_EC_X64_FP_ERROR EXCEPT_X64_FP_ERROR\r
+#define EFI_SW_EC_X64_ALIGNMENT_CHECK EXCEPT_X64_ALIGNMENT_CHECK\r
+#define EFI_SW_EC_X64_MACHINE_CHECK EXCEPT_X64_MACHINE_CHECK\r
+#define EFI_SW_EC_X64_SIMD EXCEPT_X64_SIMD\r
+///@}\r
+\r
+///\r
+/// Software Class ARM Exception Subclass Error Code definitions.\r
+/// These exceptions are derived from the debug protocol\r
+/// definitions in the EFI specification.\r
+///\r
+///@{\r
+#define EFI_SW_EC_ARM_RESET EXCEPT_ARM_RESET \r
+#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION EXCEPT_ARM_UNDEFINED_INSTRUCTION \r
+#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT EXCEPT_ARM_SOFTWARE_INTERRUPT \r
+#define EFI_SW_EC_ARM_PREFETCH_ABORT EXCEPT_ARM_PREFETCH_ABORT\r
+#define EFI_SW_EC_ARM_DATA_ABORT EXCEPT_ARM_DATA_ABORT\r
+#define EFI_SW_EC_ARM_RESERVED EXCEPT_ARM_RESERVED\r
+#define EFI_SW_EC_ARM_IRQ EXCEPT_ARM_IRQ\r
+#define EFI_SW_EC_ARM_FIQ EXCEPT_ARM_FIQ\r
+///@}\r
\r
#endif\r