MdePkg/BaseLib: Preserve EBX register and fix stack offset to LinearAddress in AsmFlu...

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / FlushCacheLine.c

diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
index 6da213a6a9676d58fc9fbc654eec23acfaddc135..7ac4af353f7bd2f2aca2ae6d7fe1eadea66ac3a1 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
+++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
@@ -1,29 +1,58 @@
 /** @file\r
   AsmFlushCacheLine function\r
 \r
-  Copyright (c) 2006, Intel Corporation<BR>\r
-  All rights reserved. This program and the accompanying materials\r
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
+  http://opensource.org/licenses/bsd-license.php.\r
 \r
   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 \r
 **/\r
 \r
-#if _MSC_EXTENSIONS\r
 \r
+\r
+\r
+/**\r
+  Flushes a cache line from all the instruction and data caches within the\r
+  coherency domain of the CPU.\r
+\r
+  Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
+  This function is only available on IA-32 and x64.\r
+\r
+  @param  LinearAddress The address of the cache line to flush. If the CPU is\r
+                        in a physical addressing mode, then LinearAddress is a\r
+                        physical address. If the CPU is in a virtual\r
+                        addressing mode, then LinearAddress is a virtual\r
+                        address.\r
+\r
+  @return LinearAddress\r
+**/\r
 VOID *\r
 EFIAPI\r
 AsmFlushCacheLine (\r
   IN      VOID                      *LinearAddress\r
   )\r
 {\r
+  //\r
+  // If the CPU does not support CLFLUSH instruction, \r
+  // then promote flush range to flush entire cache.\r
+  //\r
   _asm {\r
-    mov     eax, LinearAddress\r
+    mov     eax, 1\r
+    cpuid\r
+    test    edx, BIT19\r
+    jz      NoClflush\r
+    mov     eax, dword ptr [LinearAddress]\r
     clflush [eax]\r
+    jmp     Done\r
+NoClflush:\r
+    wbinvd\r
+Done:\r
   }\r
+  \r
+  return LinearAddress;\r
 }\r
 \r
-#endif\r