MdePkg/BaseLib: Preserve EBX register and fix stack offset to LinearAddress in AsmFlu...
authorMichael Kinney <michael.d.kinney@intel.com>
Thu, 30 Apr 2015 07:25:07 +0000 (07:25 +0000)
committererictian <erictian@Edk2>
Thu, 30 Apr 2015 07:25:07 +0000 (07:25 +0000)
The value of EBX must be preserved to follow IA32 cdecl calling convention in the assembly
implementation of AsmFlushCacheLine(). The CPUID instruction modifies the EBX register.
The EBX register value is saved onto the stack before CPUID and restored from the stack
after CPUID.

The update to the inline assembly implementation of AsmFlushCacheLine() changed the location of the
LinearAddress parameter value on the stack.  The hardcoded lookup using [esp + 4] is not correct.
Use the parameter name LinearAddress instead of the hard coded [esp + 4] stack location to prevent
this issue from occurring again if there are changes to the inline assembly in the future.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17279 6f19259b-4bc3-4df7-8a09-765794883524

MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm
MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c

index a64f96bf7e5b75fdcd7f7b58009b39049241231b..1979f6d9eb2242a5b15076f41b9500798e6b3505 100644 (file)
@@ -39,7 +39,9 @@ AsmFlushCacheLine   PROC
     ; then promote flush range to flush entire cache.\r
     ;\r
     mov     eax, 1\r
+    push    ebx\r
     cpuid\r
+    pop     ebx\r
     mov     eax, [esp + 4]\r
     test    edx, BIT19\r
     jz      @F\r
index 7ad12aba14cbbf07fb8d269ed3a4221b64bbe2be..7ac4af353f7bd2f2aca2ae6d7fe1eadea66ac3a1 100644 (file)
@@ -45,7 +45,7 @@ AsmFlushCacheLine (
     cpuid\r
     test    edx, BIT19\r
     jz      NoClflush\r
-    mov     eax, [esp + 4]\r
+    mov     eax, dword ptr [LinearAddress]\r
     clflush [eax]\r
     jmp     Done\r
 NoClflush:\r