PcAtChipsetPkg PciHostBridgeDxe: Fix build warning with GCC

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / WriteCr0.c

diff --git a/MdePkg/Library/BaseLib/Ia32/WriteCr0.c b/MdePkg/Library/BaseLib/Ia32/WriteCr0.c
index 4f2406c67eaabffd2e33756394b866d536d4e033..a39abe1194cc09e6151efe43c3841f756bcfc97c 100644 (file)
--- a/MdePkg/Library/BaseLib/Ia32/WriteCr0.c
+++ b/MdePkg/Library/BaseLib/Ia32/WriteCr0.c
@@ -1,8 +1,8 @@
 /** @file\r
   AsmWriteCr0 function\r
 \r
-  Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
-  All rights reserved. This program and the accompanying materials\r
+  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   http://opensource.org/licenses/bsd-license.php\r
@@ -12,11 +12,17 @@
 \r
 **/\r
 \r
-//\r
-// Include common header file for this module.\r
-//\r
+/**\r
+  Writes a value to Control Register 0 (CR0).\r
 \r
+  Writes and returns a new value to CR0. This function is only available on\r
+  IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r
 \r
+  @param  Value The value to write to CR0.\r
+\r
+  @return The value written to CR0.\r
+\r
+**/\r
 UINTN\r
 EFIAPI\r
 AsmWriteCr0 (\r