/** @file\r
- PEI Services Table Pointer Library for IA-32 and X64.\r
+ PEI Services Table Pointer Library for IA-32 and x64.\r
\r
According to PI specification, the peiservice pointer is stored prior at IDT\r
table in IA32 and x64 architecture.\r
- \r
- Copyright (c) 2006 - 2007, Intel Corporation.<BR>\r
- All rights reserved. This program and the accompanying materials \r
- are licensed and made available under the terms and conditions of the BSD License \r
- which accompanies this distribution. The full text of the license may be found at \r
- http://opensource.org/licenses/bsd-license.php \r
\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Library/BaseLib.h>\r
#include <Library/PeiServicesTablePointerLib.h>\r
#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
\r
/**\r
- \r
- The function returns the pointer to PeiServicee following\r
- PI1.0.\r
- \r
- For IA32, the four-bytes field immediately prior to new IDT\r
- base addres is used to save the EFI_PEI_SERVICES**.\r
- For x64, the eight-bytes field immediately prior to new IDT\r
- base addres is used to save the EFI_PEI_SERVICES**\r
- \r
+ Retrieves the cached value of the PEI Services Table pointer.\r
+\r
+ Returns the cached value of the PEI Services Table pointer in a CPU specific manner\r
+ as specified in the CPU binding section of the Platform Initialization Pre-EFI\r
+ Initialization Core Interface Specification.\r
+\r
+ If the cached PEI Services Table pointer is NULL, then ASSERT().\r
+\r
@return The pointer to PeiServices.\r
\r
**/\r
{\r
CONST EFI_PEI_SERVICES **PeiServices;\r
IA32_DESCRIPTOR Idtr;\r
- \r
+\r
AsmReadIdtr (&Idtr);\r
PeiServices = (CONST EFI_PEI_SERVICES **) (*(UINTN*)(Idtr.Base - sizeof (UINTN)));\r
ASSERT (PeiServices != NULL);\r
}\r
\r
/**\r
- \r
- The function sets the pointer to PeiServicee following\r
- PI1.0.\r
- \r
- For IA32, the four-bytes field immediately prior to new IDT\r
- base addres is used to save the EFI_PEI_SERVICES**.\r
- For x64, the eight-bytes field immediately prior to new IDT\r
- base addres is used to save the EFI_PEI_SERVICES**\r
- \r
- @param PeiServicesTablePointer The pointer to PeiServices.\r
+ Caches a pointer PEI Services Table.\r
+\r
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer\r
+ in a CPU specific manner as specified in the CPU binding section of the Platform Initialization\r
+ Pre-EFI Initialization Core Interface Specification.\r
+ The function set the pointer of PEI services immediately preceding the IDT table\r
+ according to PI specification.\r
+\r
+ If PeiServicesTablePointer is NULL, then ASSERT().\r
\r
+ @param PeiServicesTablePointer The address of PeiServices pointer.\r
**/\r
VOID\r
EFIAPI\r
IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer\r
)\r
{\r
- IA32_DESCRIPTOR Idtr;\r
- \r
+ IA32_DESCRIPTOR Idtr;\r
+\r
+ ASSERT (PeiServicesTablePointer != NULL);\r
AsmReadIdtr (&Idtr);\r
(*(UINTN*)(Idtr.Base - sizeof (UINTN))) = (UINTN)PeiServicesTablePointer;\r
}\r
\r
+/**\r
+ Perform CPU specific actions required to migrate the PEI Services Table\r
+ pointer from temporary RAM to permanent RAM.\r
+\r
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes\r
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes\r
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.\r
+ For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in\r
+ a dedicated CPU register. This means that there is no memory storage\r
+ associated with storing the PEI Services Table pointer, so no additional\r
+ migration actions are required for Itanium or ARM CPUs.\r
+\r
+ If The cached PEI Services Table pointer is NULL, then ASSERT().\r
+ If the permanent memory is allocated failed, then ASSERT().\r
+**/\r
+VOID\r
+EFIAPI\r
+MigratePeiServicesTablePointer (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ IA32_DESCRIPTOR Idtr;\r
+ EFI_PHYSICAL_ADDRESS IdtBase;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+\r
+ //\r
+ // Get PEI Services Table pointer\r
+ //\r
+ AsmReadIdtr (&Idtr);\r
+ PeiServices = (CONST EFI_PEI_SERVICES **) (*(UINTN*)(Idtr.Base - sizeof (UINTN)));\r
+ ASSERT (PeiServices != NULL);\r
+ //\r
+ // Allocate the permanent memory.\r
+ //\r
+ Status = (*PeiServices)->AllocatePages (\r
+ PeiServices,\r
+ EfiBootServicesCode,\r
+ EFI_SIZE_TO_PAGES(Idtr.Limit + 1 + sizeof (UINTN)),\r
+ &IdtBase\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ //\r
+ // Idt table needs to be migrated into memory.\r
+ //\r
+ CopyMem ((VOID *) (UINTN) IdtBase, (VOID *) (Idtr.Base - sizeof (UINTN)), Idtr.Limit + 1 + sizeof (UINTN));\r
+ Idtr.Base = (UINTN) IdtBase + sizeof (UINTN);\r
+ AsmWriteIdtr (&Idtr);\r
+\r
+ return;\r
+}\r
+\r
\r