OvmfPkg: Q35: Use correct ACPI PM control register:bit

[mirror_edk2.git] / OvmfPkg / Library / AcpiTimerLib / BaseAcpiTimerLib.c

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index 28280539b683cae4ec54902c7c34811f2dfa6ac9..58938b5d8bb8647eb9410c79fdcca9cd708015cf 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -21,8 +21,9 @@
 //\r
 // Power Management PCI Configuration Register fields\r
 //\r
-#define PMBA_RTE  BIT0\r
-#define PMIOSE    BIT0\r
+#define PMBA_RTE      BIT0\r
+#define PIIX4_PMIOSE  BIT0\r
+#define Q35_ACPI_EN   BIT7\r
 \r
 //\r
 // Offset in the Power Management Base Address to the ACPI Timer\r
@@ -49,7 +50,8 @@ AcpiTimerLibConstructor (
 {\r
   UINT16 HostBridgeDevId;\r
   UINTN Pmba;\r
-  UINTN PmRegMisc;\r
+  UINTN AcpiCtlReg;\r
+  UINT8 AcpiEnBit;\r
 \r
   //\r
   // Query Host Bridge DID to determine platform type\r
@@ -57,12 +59,14 @@ AcpiTimerLibConstructor (
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
-      Pmba      = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
+      AcpiEnBit  = PIIX4_PMIOSE;\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
-      Pmba      = POWER_MGMT_REGISTER_Q35 (0x40);\r
-      PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r
+      Pmba       = POWER_MGMT_REGISTER_Q35 (0x40);\r
+      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
+      AcpiEnBit  = Q35_ACPI_EN;\r
       break;\r
     default:\r
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
@@ -76,7 +80,7 @@ AcpiTimerLibConstructor (
   //\r
   // Check to see if the Power Management Base Address is already enabled\r
   //\r
-  if ((PciRead8 (PmRegMisc) & PMIOSE) == 0) {\r
+  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
     //\r
     // If the Power Management Base Address is not programmed,\r
     // then program the Power Management Base Address from a PCD.\r
@@ -84,9 +88,9 @@ AcpiTimerLibConstructor (
     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
 \r
     //\r
-    // Enable PMBA I/O port decodes in PMREGMISC\r
+    // Enable PMBA I/O port decodes\r
     //\r
-    PciOr8 (PmRegMisc, PMIOSE);\r
+    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
   }\r
 \r
   return RETURN_SUCCESS;\r