OvmfPkg: Modify QemuFwCfgLib to use new IoLib class library

[mirror_edk2.git] / OvmfPkg / Library / AcpiTimerLib / BaseRomAcpiTimerLib.c

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index 735dfd2e4bf90ff9e84e89002e9b99ed69ed48b5..dbbecc93c116dd3d47badb060dd5013e59c961f5 100644 (file)
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -35,6 +35,8 @@ AcpiTimerLibConstructor (
 {\r
   UINT16 HostBridgeDevId;\r
   UINTN Pmba;\r
+  UINT32 PmbaAndVal;\r
+  UINT32 PmbaOrVal;\r
   UINTN AcpiCtlReg;\r
   UINT8 AcpiEnBit;\r
 \r
@@ -45,11 +47,15 @@ AcpiTimerLibConstructor (
   switch (HostBridgeDevId) {\r
     case INTEL_82441_DEVICE_ID:\r
       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+      PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
+      PmbaOrVal  = PIIX4_PMBA_VALUE;\r
       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
       break;\r
     case INTEL_Q35_MCH_DEVICE_ID:\r
       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+      PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
+      PmbaOrVal  = ICH9_PMBASE_VALUE;\r
       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
       break;\r
@@ -68,7 +74,7 @@ AcpiTimerLibConstructor (
     // If the Power Management Base Address is not programmed,\r
     // then program it now.\r
     //\r
-    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);\r
+    PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
 \r
     //\r
     // Enable PMBA I/O port decodes\r