\r
#include <IndustryStandard/Pci.h>\r
\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
+#include <Library/DevicePathLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PciHostBridgeLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
\r
\r
+#pragma pack(1)\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
+} OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
+#pragma pack ()\r
+\r
+\r
GLOBAL_REMOVE_IF_UNREFERENCED\r
CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {\r
L"Mem", L"I/O", L"Bus"\r
};\r
\r
\r
+STATIC\r
+CONST\r
+OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {\r
+ {\r
+ {\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_DP,\r
+ {\r
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ EISA_PNP_ID(0x0A03), // HID\r
+ 0 // UID\r
+ },\r
+\r
+ {\r
+ END_DEVICE_PATH_TYPE,\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ {\r
+ END_DEVICE_PATH_LENGTH,\r
+ 0\r
+ }\r
+ }\r
+};\r
+\r
+\r
/**\r
Initialize a PCI_ROOT_BRIDGE structure.\r
\r
OUT PCI_ROOT_BRIDGE *RootBus\r
)\r
{\r
- return EFI_OUT_OF_RESOURCES;\r
+ OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;\r
+\r
+ //\r
+ // Be safe if other fields are added to PCI_ROOT_BRIDGE later.\r
+ //\r
+ ZeroMem (RootBus, sizeof *RootBus);\r
+\r
+ RootBus->Segment = 0;\r
+\r
+ RootBus->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
+ EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ RootBus->Attributes = RootBus->Supports;\r
+\r
+ RootBus->DmaAbove4G = FALSE;\r
+\r
+ RootBus->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r
+ RootBus->PMem.Base = 0;\r
+ RootBus->PMem.Limit = 0;\r
+ RootBus->PMemAbove4G.Base = 0;\r
+ RootBus->PMemAbove4G.Limit = 0;\r
+ RootBus->MemAbove4G.Base = 0;\r
+ RootBus->MemAbove4G.Limit = 0;\r
+\r
+ RootBus->Bus.Base = RootBusNumber;\r
+ RootBus->Bus.Limit = MaxSubBusNumber;\r
+ RootBus->Io.Base = PcdGet64 (PcdPciIoBase);\r
+ RootBus->Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r
+ RootBus->Mem.Base = PcdGet64 (PcdPciMmio32Base);\r
+ RootBus->Mem.Limit = PcdGet64 (PcdPciMmio32Base) +\r
+ (PcdGet64 (PcdPciMmio32Size) - 1);\r
+\r
+ RootBus->NoExtendedConfigSpace = TRUE;\r
+\r
+ DevicePath = AllocateCopyPool (sizeof mRootBridgeDevicePathTemplate,\r
+ &mRootBridgeDevicePathTemplate);\r
+ if (DevicePath == NULL) {\r
+ DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+ DevicePath->AcpiDevicePath.UID = RootBusNumber;\r
+ RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;\r
+\r
+ DEBUG ((EFI_D_INFO,\r
+ "%a: populated root bus %d, with room for %d subordinate bus(es)\n",\r
+ __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));\r
+ return EFI_SUCCESS;\r
}\r
\r
\r
IN PCI_ROOT_BRIDGE *RootBus\r
)\r
{\r
+ FreePool (RootBus->DevicePath);\r
}\r
\r
\r
UINTN Count\r
)\r
{\r
- return;\r
+ if (Bridges == NULL && Count == 0) {\r
+ return;\r
+ }\r
+ ASSERT (Bridges != NULL && Count > 0);\r
+\r
+ do {\r
+ --Count;\r
+ UninitRootBridge (&Bridges[Count]);\r
+ } while (Count > 0);\r
+\r
+ FreePool (Bridges);\r
}\r
\r
\r