/**@file\r
Memory Detection for Virtual Machines.\r
\r
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
Module Name:\r
\r
//\r
// The package level header files this module uses\r
//\r
+#include <IndustryStandard/E820.h>\r
+#include <IndustryStandard/I440FxPiix4.h>\r
+#include <IndustryStandard/Q35MchIch9.h>\r
+#include <IndustryStandard/CloudHv.h>\r
+#include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>\r
#include <PiPei.h>\r
+#include <Register/Intel/SmramSaveStateMap.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
+#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
+#include <Library/MemEncryptSevLib.h>\r
#include <Library/PcdLib.h>\r
+#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/ResourcePublicationLib.h>\r
-#include <Library/MtrrLib.h>\r
\r
+#include <Library/QemuFwCfgLib.h>\r
+#include <Library/QemuFwCfgSimpleParserLib.h>\r
#include "Platform.h"\r
-#include "Cmos.h"\r
-\r
-UINT8 mPhysMemAddressWidth;\r
\r
-UINT32\r
-GetSystemMemorySizeBelow4gb (\r
+VOID\r
+Q35TsegMbytesInitialization (\r
VOID\r
)\r
{\r
- UINT8 Cmos0x34;\r
- UINT8 Cmos0x35;\r
+ UINT16 ExtendedTsegMbytes;\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
\r
//\r
- // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r
- // * CMOS(0x35) is the high byte\r
- // * CMOS(0x34) is the low byte\r
- // * The size is specified in 64kb chunks\r
- // * Since this is memory above 16MB, the 16MB must be added\r
- // into the calculation to get the total memory size.\r
+ // Check if QEMU offers an extended TSEG.\r
//\r
+ // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r
+ // register, and reading back the register.\r
+ //\r
+ // On a QEMU machine type that does not offer an extended TSEG, the initial\r
+ // write overwrites whatever value a malicious guest OS may have placed in\r
+ // the (unimplemented) register, before entering S3 or rebooting.\r
+ // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r
+ //\r
+ // On a QEMU machine type that offers an extended TSEG, the initial write\r
+ // triggers an update to the register. Subsequently, the value read back\r
+ // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r
+ // number of megabytes.\r
+ //\r
+ PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r
+ ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r
+ if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r
+ mPlatformInfoHob.Q35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
+ return;\r
+ }\r
\r
- Cmos0x34 = (UINT8) CmosRead8 (0x34);\r
- Cmos0x35 = (UINT8) CmosRead8 (0x35);\r
-\r
- return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: QEMU offers an extended TSEG (%d MB)\n",\r
+ __FUNCTION__,\r
+ ExtendedTsegMbytes\r
+ ));\r
+ PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ mPlatformInfoHob.Q35TsegMbytes = ExtendedTsegMbytes;\r
}\r
\r
-\r
-STATIC\r
-UINT64\r
-GetSystemMemorySizeAbove4gb (\r
+VOID\r
+Q35SmramAtDefaultSmbaseInitialization (\r
+ VOID\r
)\r
{\r
- UINT32 Size;\r
- UINTN CmosIndex;\r
+ RETURN_STATUS PcdStatus;\r
\r
- //\r
- // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r
- // * CMOS(0x5d) is the most significant size byte\r
- // * CMOS(0x5c) is the middle size byte\r
- // * CMOS(0x5b) is the least significant size byte\r
- // * The size is specified in 64kb chunks\r
- //\r
+ ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
\r
- Size = 0;\r
- for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r
- Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase = FALSE;\r
+ if (FeaturePcdGet (PcdCsmEnable)) {\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: SMRAM at default SMBASE not checked due to CSM\n",\r
+ __FUNCTION__\r
+ ));\r
+ } else {\r
+ UINTN CtlReg;\r
+ UINT8 CtlRegVal;\r
+\r
+ CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);\r
+ PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);\r
+ CtlRegVal = PciRead8 (CtlReg);\r
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r
+ MCH_DEFAULT_SMBASE_IN_RAM);\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: SMRAM at default SMBASE %a\n",\r
+ __FUNCTION__,\r
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase ? "found" : "not found"\r
+ ));\r
}\r
\r
- return LShiftU64 (Size, 16);\r
+ PcdStatus = PcdSetBoolS (\r
+ PcdQ35SmramAtDefaultSmbase,\r
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase\r
+ );\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-\r
/**\r
- Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r
+ Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.\r
**/\r
VOID\r
AddressWidthInitialization (\r
- VOID\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- UINT64 FirstNonAddress;\r
+ RETURN_STATUS PcdStatus;\r
\r
- //\r
- // As guest-physical memory size grows, the permanent PEI RAM requirements\r
- // are dominated by the identity-mapping page tables built by the DXE IPL.\r
- // The DXL IPL keys off of the physical address bits advertized in the CPU\r
- // HOB. To conserve memory, we calculate the minimum address width here.\r
- //\r
- FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r
- mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r
+ PlatformAddressWidthInitialization (PlatformInfoHob);\r
\r
//\r
- // If FirstNonAddress is not an integral power of two, then we need an\r
- // additional bit.\r
+ // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r
+ // resources to 32-bit anyway. See DegradeResource() in\r
+ // "PciResourceSupport.c".\r
//\r
- if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r
- ++mPhysMemAddressWidth;\r
+ #ifdef MDE_CPU_IA32\r
+ if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
+ return;\r
}\r
\r
- //\r
- // The minimum address width is 36 (covers up to and excluding 64 GB, which\r
- // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r
- // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r
- // can simply assert that here, since 48 bits are good enough for 256 TB.\r
- //\r
- if (mPhysMemAddressWidth <= 36) {\r
- mPhysMemAddressWidth = 36;\r
+ #endif\r
+\r
+ if (PlatformInfoHob->PcdPciMmio64Size == 0) {\r
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: disabling 64-bit PCI host aperture\n",\r
+ __FUNCTION__\r
+ ));\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ }\r
+\r
+ return;\r
}\r
- ASSERT (mPhysMemAddressWidth <= 48);\r
-}\r
\r
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
+ //\r
+ // The core PciHostBridgeDxe driver will automatically add this range to\r
+ // the GCD memory space map through our PciHostBridgeLib instance; here we\r
+ // only need to set the PCDs.\r
+ //\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
+ __FUNCTION__,\r
+ PlatformInfoHob->PcdPciMmio64Base,\r
+ PlatformInfoHob->PcdPciMmio64Size\r
+ ));\r
+ }\r
+}\r
\r
/**\r
Calculate the cap for the permanent PEI memory.\r
VOID\r
)\r
{\r
- BOOLEAN Page1GSupport;\r
- UINT32 RegEax;\r
- UINT32 RegEdx;\r
- UINT32 Pml4Entries;\r
- UINT32 PdpEntries;\r
- UINTN TotalPages;\r
+ BOOLEAN Page1GSupport;\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ UINT32 Pml4Entries;\r
+ UINT32 PdpEntries;\r
+ UINTN TotalPages;\r
\r
//\r
// If DXE is 32-bit, then just return the traditional 64 MB cap.\r
//\r
-#ifdef MDE_CPU_IA32\r
+ #ifdef MDE_CPU_IA32\r
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
return SIZE_64MB;\r
}\r
-#endif\r
+\r
+ #endif\r
\r
//\r
// Dependent on physical address width, PEI memory allocations can be\r
}\r
}\r
\r
- if (mPhysMemAddressWidth <= 39) {\r
+ if (mPlatformInfoHob.PhysMemAddressWidth <= 39) {\r
Pml4Entries = 1;\r
- PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
+ PdpEntries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30);\r
ASSERT (PdpEntries <= 0x200);\r
} else {\r
- Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r
+ if (mPlatformInfoHob.PhysMemAddressWidth > 48) {\r
+ Pml4Entries = 0x200;\r
+ } else {\r
+ Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);\r
+ }\r
+\r
ASSERT (Pml4Entries <= 0x200);\r
PdpEntries = 512;\r
}\r
\r
TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
- (PdpEntries + 1) * Pml4Entries + 1;\r
+ (PdpEntries + 1) * Pml4Entries + 1;\r
ASSERT (TotalPages <= 0x40201);\r
\r
//\r
// Add 64 MB for miscellaneous allocations. Note that for\r
- // mPhysMemAddressWidth values close to 36, the cap will actually be\r
+ // PhysMemAddressWidth values close to 36, the cap will actually be\r
// dominated by this increment.\r
//\r
return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
}\r
\r
-\r
/**\r
Publish PEI core memory\r
\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS MemoryBase;\r
- UINT64 MemorySize;\r
- UINT64 LowerMemorySize;\r
- UINT32 PeiMemoryCap;\r
-\r
- if (mBootMode == BOOT_ON_S3_RESUME) {\r
- MemoryBase = PcdGet32 (PcdS3AcpiReservedMemoryBase);\r
- MemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);\r
- } else {\r
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
- if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
- //\r
- // TSEG is chipped from the end of low RAM\r
- //\r
- LowerMemorySize -= FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;\r
- }\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS MemoryBase;\r
+ UINT64 MemorySize;\r
+ UINT32 LowerMemorySize;\r
+ UINT32 PeiMemoryCap;\r
+ UINT32 S3AcpiReservedMemoryBase;\r
+ UINT32 S3AcpiReservedMemorySize;\r
+\r
+ LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (&mPlatformInfoHob);\r
+ if (mPlatformInfoHob.SmmSmramRequire) {\r
+ //\r
+ // TSEG is chipped from the end of low RAM\r
+ //\r
+ LowerMemorySize -= mPlatformInfoHob.Q35TsegMbytes * SIZE_1MB;\r
+ }\r
+\r
+ S3AcpiReservedMemoryBase = 0;\r
+ S3AcpiReservedMemorySize = 0;\r
+\r
+ //\r
+ // If S3 is supported, then the S3 permanent PEI memory is placed next,\r
+ // downwards. Its size is primarily dictated by CpuMpPei. The formula below\r
+ // is an approximation.\r
+ //\r
+ if (mPlatformInfoHob.S3Supported) {\r
+ S3AcpiReservedMemorySize = SIZE_512KB +\r
+ mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber *\r
+ PcdGet32 (PcdCpuApStackSize);\r
+ S3AcpiReservedMemoryBase = LowerMemorySize - S3AcpiReservedMemorySize;\r
+ LowerMemorySize = S3AcpiReservedMemoryBase;\r
+ }\r
+\r
+ mPlatformInfoHob.S3AcpiReservedMemoryBase = S3AcpiReservedMemoryBase;\r
+ mPlatformInfoHob.S3AcpiReservedMemorySize = S3AcpiReservedMemorySize;\r
\r
+ if (mPlatformInfoHob.BootMode == BOOT_ON_S3_RESUME) {\r
+ MemoryBase = S3AcpiReservedMemoryBase;\r
+ MemorySize = S3AcpiReservedMemorySize;\r
+ } else {\r
PeiMemoryCap = GetPeiMemoryCap ();\r
- DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
- __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "%a: PhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
+ __FUNCTION__,\r
+ mPlatformInfoHob.PhysMemAddressWidth,\r
+ PeiMemoryCap >> 10\r
+ ));\r
\r
//\r
// Determine the range of memory to use during PEI\r
// allocation HOB, and other allocations served from the permanent PEI RAM\r
// shouldn't overlap with that HOB.\r
//\r
- MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r
- PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
- PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
+ MemoryBase = mPlatformInfoHob.S3Supported && mPlatformInfoHob.SmmSmramRequire ?\r
+ PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
+ PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
MemorySize = LowerMemorySize - MemoryBase;\r
if (MemorySize > PeiMemoryCap) {\r
MemoryBase = LowerMemorySize - PeiMemoryCap;\r
}\r
\r
//\r
- // Publish this memory to the PEI Core\r
+ // MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the\r
+ // normal boot permanent PEI RAM. Regarding the S3 boot path, the S3\r
+ // permanent PEI RAM is located even higher.\r
//\r
- Status = PublishSystemMemory(MemoryBase, MemorySize);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- return Status;\r
-}\r
-\r
-\r
-/**\r
- Peform Memory Detection for QEMU / KVM\r
-\r
-**/\r
-STATIC\r
-VOID\r
-QemuInitializeRam (\r
- VOID\r
- )\r
-{\r
- UINT64 LowerMemorySize;\r
- UINT64 UpperMemorySize;\r
- MTRR_SETTINGS MtrrSettings;\r
- EFI_STATUS Status;\r
-\r
- DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));\r
-\r
- //\r
- // Determine total memory size available\r
- //\r
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
- UpperMemorySize = GetSystemMemorySizeAbove4gb ();\r
-\r
- if (mBootMode != BOOT_ON_S3_RESUME) {\r
- //\r
- // Create memory HOBs\r
- //\r
- AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
-\r
- if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
- UINT32 TsegSize;\r
-\r
- TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;\r
- AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r
- AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,\r
- TRUE);\r
- } else {\r
- AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
- }\r
-\r
- if (UpperMemorySize != 0) {\r
- AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r
- }\r
+ if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.Q35SmramAtDefaultSmbase) {\r
+ ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);\r
}\r
\r
//\r
- // We'd like to keep the following ranges uncached:\r
- // - [640 KB, 1 MB)\r
- // - [LowerMemorySize, 4 GB)\r
- //\r
- // Everything else should be WB. Unfortunately, programming the inverse (ie.\r
- // keeping the default UC, and configuring the complement set of the above as\r
- // WB) is not reliable in general, because the end of the upper RAM can have\r
- // practically any alignment, and we may not have enough variable MTRRs to\r
- // cover it exactly.\r
+ // Publish this memory to the PEI Core\r
//\r
- if (IsMtrrSupported ()) {\r
- MtrrGetAllMtrrs (&MtrrSettings);\r
-\r
- //\r
- // MTRRs disabled, fixed MTRRs disabled, default type is uncached\r
- //\r
- ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);\r
- ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);\r
- ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);\r
-\r
- //\r
- // flip default type to writeback\r
- //\r
- SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);\r
- ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);\r
- MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;\r
- MtrrSetAllMtrrs (&MtrrSettings);\r
-\r
- //\r
- // Set memory range from 640KB to 1MB to uncacheable\r
- //\r
- Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,\r
- BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);\r
- ASSERT_EFI_ERROR (Status);\r
+ Status = PublishSystemMemory (MemoryBase, MemorySize);\r
+ ASSERT_EFI_ERROR (Status);\r
\r
- //\r
- // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as\r
- // uncacheable\r
- //\r
- Status = MtrrSetMemoryAttribute (LowerMemorySize,\r
- SIZE_4GB - LowerMemorySize, CacheUncacheable);\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
+ return Status;\r
}\r
\r
/**\r
**/\r
VOID\r
InitializeRamRegions (\r
- VOID\r
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- if (!mXen) {\r
- QemuInitializeRam ();\r
- } else {\r
- XenPublishRamRegions ();\r
+ if (TdIsEnabled ()) {\r
+ PlatformTdxPublishRamRegions ();\r
+ return;\r
}\r
\r
- if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {\r
- //\r
- // This is the memory range that will be used for PEI on S3 resume\r
- //\r
- BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdS3AcpiReservedMemoryBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdS3AcpiReservedMemorySize),\r
- EfiACPIMemoryNVS\r
- );\r
-\r
- //\r
- // Cover the initial RAM area used as stack and temporary PEI heap.\r
- //\r
- // This is reserved as ACPI NVS so it can be used on S3 resume.\r
- //\r
- BuildMemoryAllocationHob (\r
- PcdGet32 (PcdOvmfSecPeiTempRamBase),\r
- PcdGet32 (PcdOvmfSecPeiTempRamSize),\r
- EfiACPIMemoryNVS\r
- );\r
-\r
- //\r
- // SEC stores its table of GUIDed section handlers here.\r
- //\r
- BuildMemoryAllocationHob (\r
- PcdGet64 (PcdGuidedExtractHandlerTableAddress),\r
- PcdGet32 (PcdGuidedExtractHandlerTableSize),\r
- EfiACPIMemoryNVS\r
- );\r
+ PlatformQemuInitializeRam (PlatformInfoHob);\r
\r
-#ifdef MDE_CPU_X64\r
- //\r
- // Reserve the initial page tables built by the reset vector code.\r
- //\r
- // Since this memory range will be used by the Reset Vector on S3\r
- // resume, it must be reserved as ACPI NVS.\r
- //\r
- BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),\r
- EfiACPIMemoryNVS\r
- );\r
-#endif\r
- }\r
+ SevInitializeRam ();\r
\r
- if (mBootMode != BOOT_ON_S3_RESUME) {\r
- //\r
- // Reserve the lock box storage area\r
- //\r
- // Since this memory range will be used on S3 resume, it must be\r
- // reserved as ACPI NVS.\r
- //\r
- // If S3 is unsupported, then various drivers might still write to the\r
- // LockBox area. We ought to prevent DXE from serving allocation requests\r
- // such that they would overlap the LockBox storage.\r
- //\r
- ZeroMem (\r
- (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r
- );\r
- BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r
- );\r
-\r
- if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
- UINT32 TsegSize;\r
-\r
- //\r
- // Make sure the TSEG area that we reported as a reserved memory resource\r
- // cannot be used for reserved memory allocations.\r
- //\r
- TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;\r
- BuildMemoryAllocationHob (\r
- GetSystemMemorySizeBelow4gb() - TsegSize,\r
- TsegSize,\r
- EfiReservedMemoryType\r
- );\r
- }\r
- }\r
+ PlatformQemuInitializeRamForS3 (PlatformInfoHob);\r
}\r
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