gGrubFileGuid = {0xb5ae312c, 0xbc8a, 0x43b1, {0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}}\r
gConfidentialComputingSecretGuid = {0xadf956ad, 0xe98c, 0x484c, {0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}}\r
gConfidentialComputingSevSnpBlobGuid = {0x067b1f5f, 0xcf26, 0x44c5, {0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}}\r
+ gUefiOvmfPkgPlatformInfoGuid = {0xdec9b486, 0x1f16, 0x47c7, {0x8f, 0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}}\r
\r
[Ppis]\r
# PPI whose presence in the PPI database signals that the TPM base address\r
#include <Library/QemuFwCfgLib.h>\r
#include <Ppi/MpServices.h>\r
#include <Register/ArchitecturalMsr.h>\r
+#include <IndustryStandard/Tdx.h>\r
\r
#include "Platform.h"\r
\r
IN OUT VOID *WorkSpace\r
)\r
{\r
- AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue);\r
+ if (TdIsEnabled ()) {\r
+ TdVmCall (TDVMCALL_WRMSR, (UINT64)MSR_IA32_FEATURE_CONTROL, mFeatureControlValue, 0, 0, 0);\r
+ } else {\r
+ AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue);\r
+ }\r
}\r
\r
/**\r
--- /dev/null
+/** @file\r
+ Initialize Intel TDX support.\r
+\r
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <IndustryStandard/Tdx.h>\r
+#include <IndustryStandard/QemuFwCfg.h>\r
+#include <Library/QemuFwCfgLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/TdxLib.h>\r
+#include <Library/PlatformInitLib.h>\r
+#include <WorkArea.h>\r
+#include <ConfidentialComputingGuestAttr.h>\r
+#include "Platform.h"\r
+\r
+/**\r
+ This Function checks if TDX is available, if present then it sets\r
+ the dynamic PCDs for Tdx guest.\r
+ **/\r
+VOID\r
+IntelTdxInitialize (\r
+ VOID\r
+ )\r
+{\r
+ #ifdef MDE_CPU_X64\r
+ RETURN_STATUS PcdStatus;\r
+\r
+ if (!TdIsEnabled ()) {\r
+ return;\r
+ }\r
+\r
+ PcdStatus = PcdSet64S (PcdConfidentialComputingGuestAttr, CCAttrIntelTdx);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
+ PcdStatus = PcdSet64S (PcdTdxSharedBitMask, TdSharedPageMask ());\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+\r
+ PcdStatus = PcdSetBoolS (PcdSetNxForStack, TRUE);\r
+ ASSERT_RETURN_ERROR (PcdStatus);\r
+ #endif\r
+}\r
\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/QemuFwCfgSimpleParserLib.h>\r
-\r
#include "Platform.h"\r
\r
VOID\r
PdpEntries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30);\r
ASSERT (PdpEntries <= 0x200);\r
} else {\r
- Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);\r
+ if (mPlatformInfoHob.PhysMemAddressWidth > 48) {\r
+ Pml4Entries = 0x200;\r
+ } else {\r
+ Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);\r
+ }\r
+\r
ASSERT (Pml4Entries <= 0x200);\r
PdpEntries = 512;\r
}\r
IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
+ if (TdIsEnabled ()) {\r
+ PlatformTdxPublishRamRegions ();\r
+ return;\r
+ }\r
+\r
PlatformQemuInitializeRam (PlatformInfoHob);\r
\r
SevInitializeRam ();\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
+/**\r
+ * @brief Builds PlatformInfo Hob\r
+ */\r
+VOID\r
+BuildPlatformInfoHob (\r
+ VOID\r
+ )\r
+{\r
+ BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, &mPlatformInfoHob, sizeof (EFI_HOB_PLATFORM_INFO));\r
+}\r
+\r
/**\r
Perform Platform PEI initialization.\r
\r
MiscInitialization (&mPlatformInfoHob);\r
}\r
\r
+ IntelTdxInitialize ();\r
InstallFeatureControlCallback ();\r
+ BuildPlatformInfoHob ();\r
\r
return EFI_SUCCESS;\r
}\r
\r
#include <IndustryStandard/E820.h>\r
#include <Library/PlatformInitLib.h>\r
+#include <IndustryStandard/IntelTdx.h>\r
\r
extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob;\r
\r
VOID\r
);\r
\r
+/**\r
+ This Function checks if TDX is available, if present then it sets\r
+ the dynamic PCDs for Tdx guest. It also builds Guid hob which contains\r
+ the Host Bridge DevId.\r
+ **/\r
+VOID\r
+IntelTdxInitialize (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ * @brief Builds PlatformInfo Hob\r
+ */\r
+VOID\r
+BuildPlatformInfoHob (\r
+ VOID\r
+ );\r
+\r
VOID\r
SevInitializeRam (\r
VOID\r
MemTypeInfo.c\r
Platform.c\r
Platform.h\r
+ IntelTdx.c\r
\r
[Packages]\r
EmbeddedPkg/EmbeddedPkg.dec\r
[Guids]\r
gEfiMemoryTypeInformationGuid\r
gFdtHobGuid\r
+ gUefiOvmfPkgPlatformInfoGuid\r
\r
[LibraryClasses]\r
BaseLib\r
gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled\r
gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr\r
gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask\r
\r
[FixedPcd]\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase\r