[mirror_edk2.git] / OvmfPkg / PlatformPei / MemDetect.c

/**@file\r
  Memory Detection for Virtual Machines.\r
\r
  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
Module Name:\r
\r
  MemDetect.c\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <IndustryStandard/E820.h>\r
#include <IndustryStandard/I440FxPiix4.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <IndustryStandard/CloudHv.h>\r
#include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>\r
#include <PiPei.h>\r
#include <Register/Intel/SmramSaveStateMap.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemEncryptSevLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/ResourcePublicationLib.h>\r
\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/QemuFwCfgSimpleParserLib.h>\r
#include "Platform.h"\r
\r
VOID\r
Q35TsegMbytesInitialization (\r
  VOID\r
  )\r
{\r
  UINT16         ExtendedTsegMbytes;\r
  RETURN_STATUS  PcdStatus;\r
\r
  ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
\r
  //\r
  // Check if QEMU offers an extended TSEG.\r
  //\r
  // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r
  // register, and reading back the register.\r
  //\r
  // On a QEMU machine type that does not offer an extended TSEG, the initial\r
  // write overwrites whatever value a malicious guest OS may have placed in\r
  // the (unimplemented) register, before entering S3 or rebooting.\r
  // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r
  //\r
  // On a QEMU machine type that offers an extended TSEG, the initial write\r
  // triggers an update to the register. Subsequently, the value read back\r
  // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r
  // number of megabytes.\r
  //\r
  PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r
  ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r
  if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r
    mPlatformInfoHob.Q35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
    return;\r
  }\r
\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "%a: QEMU offers an extended TSEG (%d MB)\n",\r
    __FUNCTION__,\r
    ExtendedTsegMbytes\r
    ));\r
  PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
  mPlatformInfoHob.Q35TsegMbytes = ExtendedTsegMbytes;\r
}\r
\r
VOID\r
Q35SmramAtDefaultSmbaseInitialization (\r
  VOID\r
  )\r
{\r
  RETURN_STATUS  PcdStatus;\r
\r
  ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
\r
  mPlatformInfoHob.Q35SmramAtDefaultSmbase = FALSE;\r
  if (FeaturePcdGet (PcdCsmEnable)) {\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "%a: SMRAM at default SMBASE not checked due to CSM\n",\r
      __FUNCTION__\r
      ));\r
  } else {\r
    UINTN  CtlReg;\r
    UINT8  CtlRegVal;\r
\r
    CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);\r
    PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);\r
    CtlRegVal                                = PciRead8 (CtlReg);\r
    mPlatformInfoHob.Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r
                                                         MCH_DEFAULT_SMBASE_IN_RAM);\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "%a: SMRAM at default SMBASE %a\n",\r
      __FUNCTION__,\r
      mPlatformInfoHob.Q35SmramAtDefaultSmbase ? "found" : "not found"\r
      ));\r
  }\r
\r
  PcdStatus = PcdSetBoolS (\r
                PcdQ35SmramAtDefaultSmbase,\r
                mPlatformInfoHob.Q35SmramAtDefaultSmbase\r
                );\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
/**\r
  Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.\r
**/\r
VOID\r
AddressWidthInitialization (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  RETURN_STATUS  PcdStatus;\r
\r
  PlatformAddressWidthInitialization (PlatformInfoHob);\r
\r
  //\r
  // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r
  // resources to 32-bit anyway. See DegradeResource() in\r
  // "PciResourceSupport.c".\r
  //\r
 #ifdef MDE_CPU_IA32\r
  if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
    return;\r
  }\r
\r
 #endif\r
\r
  if (PlatformInfoHob->PcdPciMmio64Size == 0) {\r
    if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
      DEBUG ((\r
        DEBUG_INFO,\r
        "%a: disabling 64-bit PCI host aperture\n",\r
        __FUNCTION__\r
        ));\r
      PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
      ASSERT_RETURN_ERROR (PcdStatus);\r
    }\r
\r
    return;\r
  }\r
\r
  if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
    //\r
    // The core PciHostBridgeDxe driver will automatically add this range to\r
    // the GCD memory space map through our PciHostBridgeLib instance; here we\r
    // only need to set the PCDs.\r
    //\r
    PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);\r
    ASSERT_RETURN_ERROR (PcdStatus);\r
    PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);\r
    ASSERT_RETURN_ERROR (PcdStatus);\r
\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
      __FUNCTION__,\r
      PlatformInfoHob->PcdPciMmio64Base,\r
      PlatformInfoHob->PcdPciMmio64Size\r
      ));\r
  }\r
}\r
\r
/**\r
  Calculate the cap for the permanent PEI memory.\r
**/\r
STATIC\r
UINT32\r
GetPeiMemoryCap (\r
  VOID\r
  )\r
{\r
  BOOLEAN  Page1GSupport;\r
  UINT32   RegEax;\r
  UINT32   RegEdx;\r
  UINT32   Pml4Entries;\r
  UINT32   PdpEntries;\r
  UINTN    TotalPages;\r
\r
  //\r
  // If DXE is 32-bit, then just return the traditional 64 MB cap.\r
  //\r
 #ifdef MDE_CPU_IA32\r
  if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
    return SIZE_64MB;\r
  }\r
\r
 #endif\r
\r
  //\r
  // Dependent on physical address width, PEI memory allocations can be\r
  // dominated by the page tables built for 64-bit DXE. So we key the cap off\r
  // of those. The code below is based on CreateIdentityMappingPageTables() in\r
  // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r
  //\r
  Page1GSupport = FALSE;\r
  if (PcdGetBool (PcdUse1GPageTable)) {\r
    AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
    if (RegEax >= 0x80000001) {\r
      AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
      if ((RegEdx & BIT26) != 0) {\r
        Page1GSupport = TRUE;\r
      }\r
    }\r
  }\r
\r
  if (mPlatformInfoHob.PhysMemAddressWidth <= 39) {\r
    Pml4Entries = 1;\r
    PdpEntries  = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30);\r
    ASSERT (PdpEntries <= 0x200);\r
  } else {\r
    if (mPlatformInfoHob.PhysMemAddressWidth > 48) {\r
      Pml4Entries = 0x200;\r
    } else {\r
      Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);\r
    }\r
\r
    ASSERT (Pml4Entries <= 0x200);\r
    PdpEntries = 512;\r
  }\r
\r
  TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
               (PdpEntries + 1) * Pml4Entries + 1;\r
  ASSERT (TotalPages <= 0x40201);\r
\r
  //\r
  // Add 64 MB for miscellaneous allocations. Note that for\r
  // PhysMemAddressWidth values close to 36, the cap will actually be\r
  // dominated by this increment.\r
  //\r
  return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
}\r
\r
/**\r
  Publish PEI core memory\r
\r
  @return EFI_SUCCESS     The PEIM initialized successfully.\r
\r
**/\r
EFI_STATUS\r
PublishPeiMemory (\r
  VOID\r
  )\r
{\r
  EFI_STATUS            Status;\r
  EFI_PHYSICAL_ADDRESS  MemoryBase;\r
  UINT64                MemorySize;\r
  UINT32                LowerMemorySize;\r
  UINT32                PeiMemoryCap;\r
  UINT32                S3AcpiReservedMemoryBase;\r
  UINT32                S3AcpiReservedMemorySize;\r
\r
  LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (&mPlatformInfoHob);\r
  if (mPlatformInfoHob.SmmSmramRequire) {\r
    //\r
    // TSEG is chipped from the end of low RAM\r
    //\r
    LowerMemorySize -= mPlatformInfoHob.Q35TsegMbytes * SIZE_1MB;\r
  }\r
\r
  S3AcpiReservedMemoryBase = 0;\r
  S3AcpiReservedMemorySize = 0;\r
\r
  //\r
  // If S3 is supported, then the S3 permanent PEI memory is placed next,\r
  // downwards. Its size is primarily dictated by CpuMpPei. The formula below\r
  // is an approximation.\r
  //\r
  if (mPlatformInfoHob.S3Supported) {\r
    S3AcpiReservedMemorySize = SIZE_512KB +\r
                               mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber *\r
                               PcdGet32 (PcdCpuApStackSize);\r
    S3AcpiReservedMemoryBase = LowerMemorySize - S3AcpiReservedMemorySize;\r
    LowerMemorySize          = S3AcpiReservedMemoryBase;\r
  }\r
\r
  mPlatformInfoHob.S3AcpiReservedMemoryBase = S3AcpiReservedMemoryBase;\r
  mPlatformInfoHob.S3AcpiReservedMemorySize = S3AcpiReservedMemorySize;\r
\r
  if (mPlatformInfoHob.BootMode == BOOT_ON_S3_RESUME) {\r
    MemoryBase = S3AcpiReservedMemoryBase;\r
    MemorySize = S3AcpiReservedMemorySize;\r
  } else {\r
    PeiMemoryCap = GetPeiMemoryCap ();\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "%a: PhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
      __FUNCTION__,\r
      mPlatformInfoHob.PhysMemAddressWidth,\r
      PeiMemoryCap >> 10\r
      ));\r
\r
    //\r
    // Determine the range of memory to use during PEI\r
    //\r
    // Technically we could lay the permanent PEI RAM over SEC's temporary\r
    // decompression and scratch buffer even if "secure S3" is needed, since\r
    // their lifetimes don't overlap. However, PeiFvInitialization() will cover\r
    // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory\r
    // allocation HOB, and other allocations served from the permanent PEI RAM\r
    // shouldn't overlap with that HOB.\r
    //\r
    MemoryBase = mPlatformInfoHob.S3Supported && mPlatformInfoHob.SmmSmramRequire ?\r
                 PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
                 PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
    MemorySize = LowerMemorySize - MemoryBase;\r
    if (MemorySize > PeiMemoryCap) {\r
      MemoryBase = LowerMemorySize - PeiMemoryCap;\r
      MemorySize = PeiMemoryCap;\r
    }\r
  }\r
\r
  //\r
  // MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the\r
  // normal boot permanent PEI RAM. Regarding the S3 boot path, the S3\r
  // permanent PEI RAM is located even higher.\r
  //\r
  if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.Q35SmramAtDefaultSmbase) {\r
    ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);\r
  }\r
\r
  //\r
  // Publish this memory to the PEI Core\r
  //\r
  Status = PublishSystemMemory (MemoryBase, MemorySize);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
}\r
\r
/**\r
  Publish system RAM and reserve memory regions\r
\r
**/\r
VOID\r
InitializeRamRegions (\r
  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  if (TdIsEnabled ()) {\r
    PlatformTdxPublishRamRegions ();\r
    return;\r
  }\r
\r
  PlatformQemuInitializeRam (PlatformInfoHob);\r
\r
  SevInitializeRam ();\r
\r
  PlatformQemuInitializeRamForS3 (PlatformInfoHob);\r
}\r
Commit	Line	Data
49ba9447	1	/**@file\r
	2	Memory Detection for Virtual Machines.\r
	3	\r
035ce3b3	4	Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
b26f0cf9	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
49ba9447	6	\r
	7	Module Name:\r
	8	\r
	9	MemDetect.c\r
	10	\r
	11	**/\r
	12	\r
	13	//\r
	14	// The package level header files this module uses\r
	15	//\r
1fceaddb	16	#include <IndustryStandard/E820.h>\r
49edde15	17	#include <IndustryStandard/I440FxPiix4.h>\r
d5e06444	18	#include <IndustryStandard/Q35MchIch9.h>\r
9afcd48a	19	#include <IndustryStandard/CloudHv.h>\r
82bfd2e8	20	#include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>\r
49ba9447	21	#include <PiPei.h>\r
adec2bd5	22	#include <Register/Intel/SmramSaveStateMap.h>\r
49ba9447	23	\r
	24	//\r
	25	// The Library classes this module consumes\r
	26	//\r
d5e06444	27	#include <Library/BaseLib.h>\r
6a7cba79	28	#include <Library/BaseMemoryLib.h>\r
49ba9447	29	#include <Library/DebugLib.h>\r
	30	#include <Library/HobLib.h>\r
	31	#include <Library/IoLib.h>\r
0bbed066	32	#include <Library/MemEncryptSevLib.h>\r
c1c2669c	33	#include <Library/PcdLib.h>\r
d5e06444	34	#include <Library/PciLib.h>\r
49ba9447	35	#include <Library/PeimEntryPoint.h>\r
49ba9447	36	#include <Library/ResourcePublicationLib.h>\r
10460942	37	\r
7e5b1b67	38	#include <Library/QemuFwCfgLib.h>\r
98800cce	39	#include <Library/QemuFwCfgSimpleParserLib.h>\r
49ba9447	40	#include "Platform.h"\r
49ba9447	41	\r
23bfb5c0 LE	42	VOID\r
	43	Q35TsegMbytesInitialization (\r
	44	VOID\r
	45	)\r
	46	{\r
ac0a286f MK	47	UINT16 ExtendedTsegMbytes;\r
ac0a286f MK	48	RETURN_STATUS PcdStatus;\r
d5e06444	49	\r
9a9b33b3	50	ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
d5e06444 LE	51	\r
	52	//\r
	53	// Check if QEMU offers an extended TSEG.\r
	54	//\r
	55	// This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r
	56	// register, and reading back the register.\r
	57	//\r
	58	// On a QEMU machine type that does not offer an extended TSEG, the initial\r
	59	// write overwrites whatever value a malicious guest OS may have placed in\r
	60	// the (unimplemented) register, before entering S3 or rebooting.\r
	61	// Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r
	62	//\r
	63	// On a QEMU machine type that offers an extended TSEG, the initial write\r
	64	// triggers an update to the register. Subsequently, the value read back\r
	65	// (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r
	66	// number of megabytes.\r
	67	//\r
	68	PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r
	69	ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r
	70	if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r
9a9b33b3	71	mPlatformInfoHob.Q35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
d5e06444 LE	72	return;\r
	73	}\r
	74	\r
	75	DEBUG ((\r
	76	DEBUG_INFO,\r
	77	"%a: QEMU offers an extended TSEG (%d MB)\n",\r
	78	__FUNCTION__,\r
	79	ExtendedTsegMbytes\r
	80	));\r
	81	PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r
	82	ASSERT_RETURN_ERROR (PcdStatus);\r
9a9b33b3	83	mPlatformInfoHob.Q35TsegMbytes = ExtendedTsegMbytes;\r
23bfb5c0 LE	84	}\r
23bfb5c0 LE	85	\r
73974f80 LE	86	VOID\r
	87	Q35SmramAtDefaultSmbaseInitialization (\r
	88	VOID\r
	89	)\r
	90	{\r
ac0a286f	91	RETURN_STATUS PcdStatus;\r
73974f80	92	\r
9a9b33b3	93	ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
73974f80	94	\r
9a9b33b3	95	mPlatformInfoHob.Q35SmramAtDefaultSmbase = FALSE;\r
75839f97	96	if (FeaturePcdGet (PcdCsmEnable)) {\r
ac0a286f MK	97	DEBUG ((\r
	98	DEBUG_INFO,\r
	99	"%a: SMRAM at default SMBASE not checked due to CSM\n",\r
	100	__FUNCTION__\r
	101	));\r
75839f97	102	} else {\r
ac0a286f MK	103	UINTN CtlReg;\r
ac0a286f MK	104	UINT8 CtlRegVal;\r
75839f97 LE	105	\r
	106	CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);\r
	107	PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);\r
9a9b33b3 MX	108	CtlRegVal = PciRead8 (CtlReg);\r
	109	mPlatformInfoHob.Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r
	110	MCH_DEFAULT_SMBASE_IN_RAM);\r
ac0a286f MK	111	DEBUG ((\r
	112	DEBUG_INFO,\r
	113	"%a: SMRAM at default SMBASE %a\n",\r
	114	__FUNCTION__,\r
9a9b33b3	115	mPlatformInfoHob.Q35SmramAtDefaultSmbase ? "found" : "not found"\r
ac0a286f	116	));\r
75839f97 LE	117	}\r
75839f97 LE	118	\r
ac0a286f MK	119	PcdStatus = PcdSetBoolS (\r
ac0a286f MK	120	PcdQ35SmramAtDefaultSmbase,\r
9a9b33b3	121	mPlatformInfoHob.Q35SmramAtDefaultSmbase\r
ac0a286f	122	);\r
73974f80 LE	123	ASSERT_RETURN_ERROR (PcdStatus);\r
	124	}\r
	125	\r
3dd47f95 MX	126	/**\r
	127	Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.\r
	128	**/\r
	129	VOID\r
	130	AddressWidthInitialization (\r
	131	IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
	132	)\r
	133	{\r
	134	RETURN_STATUS PcdStatus;\r
	135	\r
	136	PlatformAddressWidthInitialization (PlatformInfoHob);\r
	137	\r
	138	//\r
	139	// If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r
	140	// resources to 32-bit anyway. See DegradeResource() in\r
	141	// "PciResourceSupport.c".\r
	142	//\r
	143	#ifdef MDE_CPU_IA32\r
	144	if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
	145	return;\r
	146	}\r
	147	\r
	148	#endif\r
	149	\r
	150	if (PlatformInfoHob->PcdPciMmio64Size == 0) {\r
	151	if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
	152	DEBUG ((\r
	153	DEBUG_INFO,\r
	154	"%a: disabling 64-bit PCI host aperture\n",\r
	155	__FUNCTION__\r
	156	));\r
	157	PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
	158	ASSERT_RETURN_ERROR (PcdStatus);\r
	159	}\r
	160	\r
	161	return;\r
	162	}\r
	163	\r
	164	if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
	165	//\r
	166	// The core PciHostBridgeDxe driver will automatically add this range to\r
	167	// the GCD memory space map through our PciHostBridgeLib instance; here we\r
	168	// only need to set the PCDs.\r
	169	//\r
	170	PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);\r
	171	ASSERT_RETURN_ERROR (PcdStatus);\r
	172	PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);\r
	173	ASSERT_RETURN_ERROR (PcdStatus);\r
	174	\r
	175	DEBUG ((\r
	176	DEBUG_INFO,\r
	177	"%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
	178	__FUNCTION__,\r
	179	PlatformInfoHob->PcdPciMmio64Base,\r
	180	PlatformInfoHob->PcdPciMmio64Size\r
	181	));\r
	182	}\r
	183	}\r
	184	\r
bc89fe48 LE	185	/**\r
	186	Calculate the cap for the permanent PEI memory.\r
	187	**/\r
	188	STATIC\r
	189	UINT32\r
	190	GetPeiMemoryCap (\r
	191	VOID\r
	192	)\r
	193	{\r
ac0a286f MK	194	BOOLEAN Page1GSupport;\r
	195	UINT32 RegEax;\r
	196	UINT32 RegEdx;\r
	197	UINT32 Pml4Entries;\r
	198	UINT32 PdpEntries;\r
	199	UINTN TotalPages;\r
bc89fe48 LE	200	\r
	201	//\r
	202	// If DXE is 32-bit, then just return the traditional 64 MB cap.\r
	203	//\r
ac0a286f	204	#ifdef MDE_CPU_IA32\r
bc89fe48 LE	205	if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
	206	return SIZE_64MB;\r
	207	}\r
ac0a286f MK	208	\r
ac0a286f MK	209	#endif\r
bc89fe48 LE	210	\r
	211	//\r
	212	// Dependent on physical address width, PEI memory allocations can be\r
	213	// dominated by the page tables built for 64-bit DXE. So we key the cap off\r
	214	// of those. The code below is based on CreateIdentityMappingPageTables() in\r
	215	// "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r
	216	//\r
	217	Page1GSupport = FALSE;\r
	218	if (PcdGetBool (PcdUse1GPageTable)) {\r
	219	AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
	220	if (RegEax >= 0x80000001) {\r
	221	AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
	222	if ((RegEdx & BIT26) != 0) {\r
	223	Page1GSupport = TRUE;\r
	224	}\r
	225	}\r
	226	}\r
	227	\r
9a9b33b3	228	if (mPlatformInfoHob.PhysMemAddressWidth <= 39) {\r
bc89fe48	229	Pml4Entries = 1;\r
9a9b33b3	230	PdpEntries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30);\r
bc89fe48 LE	231	ASSERT (PdpEntries <= 0x200);\r
bc89fe48 LE	232	} else {\r
cf17156d MX	233	if (mPlatformInfoHob.PhysMemAddressWidth > 48) {\r
	234	Pml4Entries = 0x200;\r
	235	} else {\r
	236	Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);\r
	237	}\r
	238	\r
bc89fe48 LE	239	ASSERT (Pml4Entries <= 0x200);\r
	240	PdpEntries = 512;\r
	241	}\r
	242	\r
	243	TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
ac0a286f	244	(PdpEntries + 1) * Pml4Entries + 1;\r
bc89fe48 LE	245	ASSERT (TotalPages <= 0x40201);\r
	246	\r
	247	//\r
	248	// Add 64 MB for miscellaneous allocations. Note that for\r
3dd47f95	249	// PhysMemAddressWidth values close to 36, the cap will actually be\r
bc89fe48 LE	250	// dominated by this increment.\r
	251	//\r
	252	return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
	253	}\r
	254	\r
36658fff WL	255	/**\r
	256	Publish PEI core memory\r
	257	\r
	258	@return EFI_SUCCESS The PEIM initialized successfully.\r
	259	\r
	260	**/\r
	261	EFI_STATUS\r
	262	PublishPeiMemory (\r
	263	VOID\r
	264	)\r
	265	{\r
ac0a286f MK	266	EFI_STATUS Status;\r
	267	EFI_PHYSICAL_ADDRESS MemoryBase;\r
	268	UINT64 MemorySize;\r
	269	UINT32 LowerMemorySize;\r
	270	UINT32 PeiMemoryCap;\r
9a9b33b3 MX	271	UINT32 S3AcpiReservedMemoryBase;\r
9a9b33b3 MX	272	UINT32 S3AcpiReservedMemorySize;\r
36658fff	273	\r
e5103262	274	LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (&mPlatformInfoHob);\r
9a9b33b3	275	if (mPlatformInfoHob.SmmSmramRequire) {\r
45d87081 LE	276	//\r
	277	// TSEG is chipped from the end of low RAM\r
	278	//\r
9a9b33b3	279	LowerMemorySize -= mPlatformInfoHob.Q35TsegMbytes * SIZE_1MB;\r
45d87081 LE	280	}\r
45d87081 LE	281	\r
9a9b33b3 MX	282	S3AcpiReservedMemoryBase = 0;\r
	283	S3AcpiReservedMemorySize = 0;\r
	284	\r
45d87081 LE	285	//\r
	286	// If S3 is supported, then the S3 permanent PEI memory is placed next,\r
	287	// downwards. Its size is primarily dictated by CpuMpPei. The formula below\r
	288	// is an approximation.\r
	289	//\r
9a9b33b3 MX	290	if (mPlatformInfoHob.S3Supported) {\r
	291	S3AcpiReservedMemorySize = SIZE_512KB +\r
	292	mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber *\r
	293	PcdGet32 (PcdCpuApStackSize);\r
	294	S3AcpiReservedMemoryBase = LowerMemorySize - S3AcpiReservedMemorySize;\r
	295	LowerMemorySize = S3AcpiReservedMemoryBase;\r
45d87081 LE	296	}\r
45d87081 LE	297	\r
9a9b33b3 MX	298	mPlatformInfoHob.S3AcpiReservedMemoryBase = S3AcpiReservedMemoryBase;\r
	299	mPlatformInfoHob.S3AcpiReservedMemorySize = S3AcpiReservedMemorySize;\r
	300	\r
	301	if (mPlatformInfoHob.BootMode == BOOT_ON_S3_RESUME) {\r
	302	MemoryBase = S3AcpiReservedMemoryBase;\r
	303	MemorySize = S3AcpiReservedMemorySize;\r
8e54500f	304	} else {\r
bc89fe48	305	PeiMemoryCap = GetPeiMemoryCap ();\r
ac0a286f MK	306	DEBUG ((\r
ac0a286f MK	307	DEBUG_INFO,\r
3dd47f95	308	"%a: PhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
ac0a286f	309	__FUNCTION__,\r
9a9b33b3	310	mPlatformInfoHob.PhysMemAddressWidth,\r
ac0a286f MK	311	PeiMemoryCap >> 10\r
ac0a286f MK	312	));\r
bc89fe48	313	\r
8e54500f JJ	314	//\r
	315	// Determine the range of memory to use during PEI\r
	316	//\r
efb0f16e LE	317	// Technically we could lay the permanent PEI RAM over SEC's temporary\r
	318	// decompression and scratch buffer even if "secure S3" is needed, since\r
	319	// their lifetimes don't overlap. However, PeiFvInitialization() will cover\r
	320	// RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory\r
	321	// allocation HOB, and other allocations served from the permanent PEI RAM\r
	322	// shouldn't overlap with that HOB.\r
	323	//\r
9a9b33b3	324	MemoryBase = mPlatformInfoHob.S3Supported && mPlatformInfoHob.SmmSmramRequire ?\r
ac0a286f MK	325	PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
ac0a286f MK	326	PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
8e54500f	327	MemorySize = LowerMemorySize - MemoryBase;\r
bc89fe48 LE	328	if (MemorySize > PeiMemoryCap) {\r
	329	MemoryBase = LowerMemorySize - PeiMemoryCap;\r
	330	MemorySize = PeiMemoryCap;\r
8e54500f	331	}\r
36658fff WL	332	}\r
36658fff WL	333	\r
adec2bd5 LE	334	//\r
	335	// MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the\r
	336	// normal boot permanent PEI RAM. Regarding the S3 boot path, the S3\r
	337	// permanent PEI RAM is located even higher.\r
	338	//\r
9a9b33b3	339	if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.Q35SmramAtDefaultSmbase) {\r
adec2bd5 LE	340	ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);\r
	341	}\r
	342	\r
36658fff WL	343	//\r
	344	// Publish this memory to the PEI Core\r
	345	//\r
ac0a286f	346	Status = PublishSystemMemory (MemoryBase, MemorySize);\r
36658fff WL	347	ASSERT_EFI_ERROR (Status);\r
	348	\r
	349	return Status;\r
	350	}\r
	351	\r
e5103262 MX	352	/**\r
	353	Publish system RAM and reserve memory regions\r
	354	\r
	355	**/\r
	356	VOID\r
	357	InitializeRamRegions (\r
	358	IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
	359	)\r
	360	{\r
cf17156d MX	361	if (TdIsEnabled ()) {\r
	362	PlatformTdxPublishRamRegions ();\r
	363	return;\r
	364	}\r
	365	\r
e5103262 MX	366	PlatformQemuInitializeRam (PlatformInfoHob);\r
	367	\r
	368	SevInitializeRam ();\r
	369	\r
	370	PlatformQemuInitializeRamForS3 (PlatformInfoHob);\r
	371	}\r