#include <IndustryStandard/I440FxPiix4.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <IndustryStandard/CloudHv.h>\r
+#include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>\r
#include <PiPei.h>\r
#include <Register/Intel/SmramSaveStateMap.h>\r
\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/ResourcePublicationLib.h>\r
-#include <Library/MtrrLib.h>\r
+\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/QemuFwCfgSimpleParserLib.h>\r
-\r
#include "Platform.h"\r
\r
-UINT8 mPhysMemAddressWidth;\r
-\r
-STATIC UINT32 mS3AcpiReservedMemoryBase;\r
-STATIC UINT32 mS3AcpiReservedMemorySize;\r
-\r
-STATIC UINT16 mQ35TsegMbytes;\r
-\r
-BOOLEAN mQ35SmramAtDefaultSmbase;\r
-\r
-UINT32 mQemuUc32Base;\r
-\r
VOID\r
Q35TsegMbytesInitialization (\r
VOID\r
UINT16 ExtendedTsegMbytes;\r
RETURN_STATUS PcdStatus;\r
\r
- ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
+ ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
\r
//\r
// Check if QEMU offers an extended TSEG.\r
PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r
ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r
if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r
- mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
+ mPlatformInfoHob.Q35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
return;\r
}\r
\r
));\r
PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
- mQ35TsegMbytes = ExtendedTsegMbytes;\r
+ mPlatformInfoHob.Q35TsegMbytes = ExtendedTsegMbytes;\r
}\r
\r
VOID\r
{\r
RETURN_STATUS PcdStatus;\r
\r
- ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
+ ASSERT (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
\r
- mQ35SmramAtDefaultSmbase = FALSE;\r
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase = FALSE;\r
if (FeaturePcdGet (PcdCsmEnable)) {\r
DEBUG ((\r
DEBUG_INFO,\r
\r
CtlReg = DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL);\r
PciWrite8 (CtlReg, MCH_DEFAULT_SMBASE_QUERY);\r
- CtlRegVal = PciRead8 (CtlReg);\r
- mQ35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r
- MCH_DEFAULT_SMBASE_IN_RAM);\r
+ CtlRegVal = PciRead8 (CtlReg);\r
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase = (BOOLEAN)(CtlRegVal ==\r
+ MCH_DEFAULT_SMBASE_IN_RAM);\r
DEBUG ((\r
DEBUG_INFO,\r
"%a: SMRAM at default SMBASE %a\n",\r
__FUNCTION__,\r
- mQ35SmramAtDefaultSmbase ? "found" : "not found"\r
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase ? "found" : "not found"\r
));\r
}\r
\r
PcdStatus = PcdSetBoolS (\r
PcdQ35SmramAtDefaultSmbase,\r
- mQ35SmramAtDefaultSmbase\r
+ mPlatformInfoHob.Q35SmramAtDefaultSmbase\r
);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-VOID\r
-QemuUc32BaseInitialization (\r
- VOID\r
- )\r
-{\r
- UINT32 LowerMemorySize;\r
- UINT32 Uc32Size;\r
-\r
- if (mHostBridgeDevId == 0xffff /* microvm */) {\r
- return;\r
- }\r
-\r
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
- //\r
- // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,\r
- // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for\r
- // setting PcdPciExpressBaseAddress such that describing the\r
- // [PcdPciExpressBaseAddress, 4GB) range require a very small number of\r
- // variable MTRRs (preferably 1 or 2).\r
- //\r
- ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);\r
- mQemuUc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);\r
- return;\r
- }\r
-\r
- if (mHostBridgeDevId == CLOUDHV_DEVICE_ID) {\r
- Uc32Size = CLOUDHV_MMIO_HOLE_SIZE;\r
- mQemuUc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;\r
- return;\r
- }\r
-\r
- ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);\r
- //\r
- // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one\r
- // variable MTRR suffices by truncating the size to a whole power of two,\r
- // while keeping the end affixed to 4GB. This will round the base up.\r
- //\r
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
- Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));\r
- mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);\r
- //\r
- // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.\r
- // Therefore mQemuUc32Base is at least 2GB.\r
- //\r
- ASSERT (mQemuUc32Base >= BASE_2GB);\r
-\r
- if (mQemuUc32Base != LowerMemorySize) {\r
- DEBUG ((\r
- DEBUG_VERBOSE,\r
- "%a: rounded UC32 base from 0x%x up to 0x%x, for "\r
- "an UC32 size of 0x%x\n",\r
- __FUNCTION__,\r
- LowerMemorySize,\r
- mQemuUc32Base,\r
- Uc32Size\r
- ));\r
- }\r
-}\r
-\r
-/**\r
- Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside\r
- of the 32-bit address range.\r
-\r
- Find the highest exclusive >=4GB RAM address, or produce memory resource\r
- descriptor HOBs for RAM entries that start at or above 4GB.\r
-\r
- @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()\r
- produces memory resource descriptor HOBs for RAM\r
- entries that start at or above 4GB.\r
-\r
- Otherwise, MaxAddress holds the highest exclusive\r
- >=4GB RAM address on output. If QEMU's fw_cfg E820\r
- RAM map contains no RAM entry that starts outside of\r
- the 32-bit address range, then MaxAddress is exactly\r
- 4GB on output.\r
-\r
- @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.\r
-\r
- @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a\r
- whole multiple of sizeof(EFI_E820_ENTRY64). No\r
- RAM entry was processed.\r
-\r
- @return Error codes from QemuFwCfgFindFile(). No RAM\r
- entry was processed.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-ScanOrAdd64BitE820Ram (\r
- IN BOOLEAN AddHighHob,\r
- OUT UINT64 *LowMemory OPTIONAL,\r
- OUT UINT64 *MaxAddress OPTIONAL\r
- )\r
-{\r
- EFI_STATUS Status;\r
- FIRMWARE_CONFIG_ITEM FwCfgItem;\r
- UINTN FwCfgSize;\r
- EFI_E820_ENTRY64 E820Entry;\r
- UINTN Processed;\r
-\r
- Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
-\r
- if (FwCfgSize % sizeof E820Entry != 0) {\r
- return EFI_PROTOCOL_ERROR;\r
- }\r
-\r
- if (LowMemory != NULL) {\r
- *LowMemory = 0;\r
- }\r
-\r
- if (MaxAddress != NULL) {\r
- *MaxAddress = BASE_4GB;\r
- }\r
-\r
- QemuFwCfgSelectItem (FwCfgItem);\r
- for (Processed = 0; Processed < FwCfgSize; Processed += sizeof E820Entry) {\r
- QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry);\r
- DEBUG ((\r
- DEBUG_VERBOSE,\r
- "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",\r
- __FUNCTION__,\r
- E820Entry.BaseAddr,\r
- E820Entry.Length,\r
- E820Entry.Type\r
- ));\r
- if (E820Entry.Type == EfiAcpiAddressRangeMemory) {\r
- if (AddHighHob && (E820Entry.BaseAddr >= BASE_4GB)) {\r
- UINT64 Base;\r
- UINT64 End;\r
-\r
- //\r
- // Round up the start address, and round down the end address.\r
- //\r
- Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);\r
- End = (E820Entry.BaseAddr + E820Entry.Length) &\r
- ~(UINT64)EFI_PAGE_MASK;\r
- if (Base < End) {\r
- AddMemoryRangeHob (Base, End);\r
- DEBUG ((\r
- DEBUG_VERBOSE,\r
- "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",\r
- __FUNCTION__,\r
- Base,\r
- End\r
- ));\r
- }\r
- }\r
-\r
- if (MaxAddress || LowMemory) {\r
- UINT64 Candidate;\r
-\r
- Candidate = E820Entry.BaseAddr + E820Entry.Length;\r
- if (MaxAddress && (Candidate > *MaxAddress)) {\r
- *MaxAddress = Candidate;\r
- DEBUG ((\r
- DEBUG_VERBOSE,\r
- "%a: MaxAddress=0x%Lx\n",\r
- __FUNCTION__,\r
- *MaxAddress\r
- ));\r
- }\r
-\r
- if (LowMemory && (Candidate > *LowMemory) && (Candidate < BASE_4GB)) {\r
- *LowMemory = Candidate;\r
- DEBUG ((\r
- DEBUG_VERBOSE,\r
- "%a: LowMemory=0x%Lx\n",\r
- __FUNCTION__,\r
- *LowMemory\r
- ));\r
- }\r
- }\r
- }\r
- }\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-UINT32\r
-GetSystemMemorySizeBelow4gb (\r
- VOID\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT64 LowerMemorySize = 0;\r
-\r
- Status = ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL);\r
- ASSERT_EFI_ERROR (Status);\r
- ASSERT (LowerMemorySize > 0);\r
- return (UINT32)LowerMemorySize;\r
-}\r
-\r
/**\r
- Return the highest address that DXE could possibly use, plus one.\r
+ Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.\r
**/\r
-STATIC\r
-UINT64\r
-GetFirstNonAddress (\r
- VOID\r
+VOID\r
+AddressWidthInitialization (\r
+ IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- UINT64 FirstNonAddress;\r
- UINT64 Pci64Base, Pci64Size;\r
- UINT32 FwCfgPciMmio64Mb;\r
- EFI_STATUS Status;\r
- FIRMWARE_CONFIG_ITEM FwCfgItem;\r
- UINTN FwCfgSize;\r
- UINT64 HotPlugMemoryEnd;\r
- RETURN_STATUS PcdStatus;\r
-\r
- //\r
- // set FirstNonAddress to suppress incorrect compiler/analyzer warnings\r
- //\r
- FirstNonAddress = 0;\r
+ RETURN_STATUS PcdStatus;\r
\r
- //\r
- // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM\r
- // address from it. This can express an address >= 4GB+1TB.\r
- //\r
- Status = ScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress);\r
- if (EFI_ERROR (Status)) {\r
- FirstNonAddress = BASE_4GB;\r
- }\r
+ PlatformAddressWidthInitialization (PlatformInfoHob);\r
\r
//\r
// If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r
//\r
#ifdef MDE_CPU_IA32\r
if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
- return FirstNonAddress;\r
+ return;\r
}\r
\r
#endif\r
\r
- //\r
- // Otherwise, in order to calculate the highest address plus one, we must\r
- // consider the 64-bit PCI host aperture too. Fetch the default size.\r
- //\r
- Pci64Size = PcdGet64 (PcdPciMmio64Size);\r
-\r
- //\r
- // See if the user specified the number of megabytes for the 64-bit PCI host\r
- // aperture. Accept an aperture size up to 16TB.\r
- //\r
- // As signaled by the "X-" prefix, this knob is experimental, and might go\r
- // away at any time.\r
- //\r
- Status = QemuFwCfgParseUint32 (\r
- "opt/ovmf/X-PciMmio64Mb",\r
- FALSE,\r
- &FwCfgPciMmio64Mb\r
- );\r
- switch (Status) {\r
- case EFI_UNSUPPORTED:\r
- case EFI_NOT_FOUND:\r
- break;\r
- case EFI_SUCCESS:\r
- if (FwCfgPciMmio64Mb <= 0x1000000) {\r
- Pci64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);\r
- break;\r
- }\r
-\r
- //\r
- // fall through\r
- //\r
- default:\r
- DEBUG ((\r
- DEBUG_WARN,\r
- "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r
- __FUNCTION__\r
- ));\r
- break;\r
- }\r
-\r
- if (Pci64Size == 0) {\r
- if (mBootMode != BOOT_ON_S3_RESUME) {\r
+ if (PlatformInfoHob->PcdPciMmio64Size == 0) {\r
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
DEBUG ((\r
DEBUG_INFO,\r
"%a: disabling 64-bit PCI host aperture\n",\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
- //\r
- // There's nothing more to do; the amount of memory above 4GB fully\r
- // determines the highest address plus one. The memory hotplug area (see\r
- // below) plays no role for the firmware in this case.\r
- //\r
- return FirstNonAddress;\r
- }\r
-\r
- //\r
- // The "etc/reserved-memory-end" fw_cfg file, when present, contains an\r
- // absolute, exclusive end address for the memory hotplug area. This area\r
- // starts right at the end of the memory above 4GB. The 64-bit PCI host\r
- // aperture must be placed above it.\r
- //\r
- Status = QemuFwCfgFindFile (\r
- "etc/reserved-memory-end",\r
- &FwCfgItem,\r
- &FwCfgSize\r
- );\r
- if (!EFI_ERROR (Status) && (FwCfgSize == sizeof HotPlugMemoryEnd)) {\r
- QemuFwCfgSelectItem (FwCfgItem);\r
- QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);\r
- DEBUG ((\r
- DEBUG_VERBOSE,\r
- "%a: HotPlugMemoryEnd=0x%Lx\n",\r
- __FUNCTION__,\r
- HotPlugMemoryEnd\r
- ));\r
-\r
- ASSERT (HotPlugMemoryEnd >= FirstNonAddress);\r
- FirstNonAddress = HotPlugMemoryEnd;\r
+ return;\r
}\r
\r
- //\r
- // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r
- // that the host can map it with 1GB hugepages. Follow suit.\r
- //\r
- Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r
- Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);\r
-\r
- //\r
- // The 64-bit PCI host aperture should also be "naturally" aligned. The\r
- // alignment is determined by rounding the size of the aperture down to the\r
- // next smaller or equal power of two. That is, align the aperture by the\r
- // largest BAR size that can fit into it.\r
- //\r
- Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));\r
-\r
- if (mBootMode != BOOT_ON_S3_RESUME) {\r
+ if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
//\r
// The core PciHostBridgeDxe driver will automatically add this range to\r
// the GCD memory space map through our PciHostBridgeLib instance; here we\r
// only need to set the PCDs.\r
//\r
- PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
- PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r
+ PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
\r
DEBUG ((\r
DEBUG_INFO,\r
"%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
__FUNCTION__,\r
- Pci64Base,\r
- Pci64Size\r
+ PlatformInfoHob->PcdPciMmio64Base,\r
+ PlatformInfoHob->PcdPciMmio64Size\r
));\r
}\r
-\r
- //\r
- // The useful address space ends with the 64-bit PCI host aperture.\r
- //\r
- FirstNonAddress = Pci64Base + Pci64Size;\r
- return FirstNonAddress;\r
-}\r
-\r
-/**\r
- Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r
-**/\r
-VOID\r
-AddressWidthInitialization (\r
- VOID\r
- )\r
-{\r
- UINT64 FirstNonAddress;\r
-\r
- //\r
- // As guest-physical memory size grows, the permanent PEI RAM requirements\r
- // are dominated by the identity-mapping page tables built by the DXE IPL.\r
- // The DXL IPL keys off of the physical address bits advertized in the CPU\r
- // HOB. To conserve memory, we calculate the minimum address width here.\r
- //\r
- FirstNonAddress = GetFirstNonAddress ();\r
- mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r
-\r
- //\r
- // If FirstNonAddress is not an integral power of two, then we need an\r
- // additional bit.\r
- //\r
- if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r
- ++mPhysMemAddressWidth;\r
- }\r
-\r
- //\r
- // The minimum address width is 36 (covers up to and excluding 64 GB, which\r
- // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r
- // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r
- // can simply assert that here, since 48 bits are good enough for 256 TB.\r
- //\r
- if (mPhysMemAddressWidth <= 36) {\r
- mPhysMemAddressWidth = 36;\r
- }\r
-\r
- ASSERT (mPhysMemAddressWidth <= 48);\r
}\r
\r
/**\r
}\r
}\r
\r
- if (mPhysMemAddressWidth <= 39) {\r
+ if (mPlatformInfoHob.PhysMemAddressWidth <= 39) {\r
Pml4Entries = 1;\r
- PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
+ PdpEntries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30);\r
ASSERT (PdpEntries <= 0x200);\r
} else {\r
- Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r
+ if (mPlatformInfoHob.PhysMemAddressWidth > 48) {\r
+ Pml4Entries = 0x200;\r
+ } else {\r
+ Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39);\r
+ }\r
+\r
ASSERT (Pml4Entries <= 0x200);\r
PdpEntries = 512;\r
}\r
\r
//\r
// Add 64 MB for miscellaneous allocations. Note that for\r
- // mPhysMemAddressWidth values close to 36, the cap will actually be\r
+ // PhysMemAddressWidth values close to 36, the cap will actually be\r
// dominated by this increment.\r
//\r
return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
UINT64 MemorySize;\r
UINT32 LowerMemorySize;\r
UINT32 PeiMemoryCap;\r
+ UINT32 S3AcpiReservedMemoryBase;\r
+ UINT32 S3AcpiReservedMemorySize;\r
\r
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
- if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (&mPlatformInfoHob);\r
+ if (mPlatformInfoHob.SmmSmramRequire) {\r
//\r
// TSEG is chipped from the end of low RAM\r
//\r
- LowerMemorySize -= mQ35TsegMbytes * SIZE_1MB;\r
+ LowerMemorySize -= mPlatformInfoHob.Q35TsegMbytes * SIZE_1MB;\r
}\r
\r
+ S3AcpiReservedMemoryBase = 0;\r
+ S3AcpiReservedMemorySize = 0;\r
+\r
//\r
// If S3 is supported, then the S3 permanent PEI memory is placed next,\r
// downwards. Its size is primarily dictated by CpuMpPei. The formula below\r
// is an approximation.\r
//\r
- if (mS3Supported) {\r
- mS3AcpiReservedMemorySize = SIZE_512KB +\r
- mMaxCpuCount *\r
- PcdGet32 (PcdCpuApStackSize);\r
- mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;\r
- LowerMemorySize = mS3AcpiReservedMemoryBase;\r
+ if (mPlatformInfoHob.S3Supported) {\r
+ S3AcpiReservedMemorySize = SIZE_512KB +\r
+ mPlatformInfoHob.PcdCpuMaxLogicalProcessorNumber *\r
+ PcdGet32 (PcdCpuApStackSize);\r
+ S3AcpiReservedMemoryBase = LowerMemorySize - S3AcpiReservedMemorySize;\r
+ LowerMemorySize = S3AcpiReservedMemoryBase;\r
}\r
\r
- if (mBootMode == BOOT_ON_S3_RESUME) {\r
- MemoryBase = mS3AcpiReservedMemoryBase;\r
- MemorySize = mS3AcpiReservedMemorySize;\r
+ mPlatformInfoHob.S3AcpiReservedMemoryBase = S3AcpiReservedMemoryBase;\r
+ mPlatformInfoHob.S3AcpiReservedMemorySize = S3AcpiReservedMemorySize;\r
+\r
+ if (mPlatformInfoHob.BootMode == BOOT_ON_S3_RESUME) {\r
+ MemoryBase = S3AcpiReservedMemoryBase;\r
+ MemorySize = S3AcpiReservedMemorySize;\r
} else {\r
PeiMemoryCap = GetPeiMemoryCap ();\r
DEBUG ((\r
DEBUG_INFO,\r
- "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
+ "%a: PhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
__FUNCTION__,\r
- mPhysMemAddressWidth,\r
+ mPlatformInfoHob.PhysMemAddressWidth,\r
PeiMemoryCap >> 10\r
));\r
\r
// allocation HOB, and other allocations served from the permanent PEI RAM\r
// shouldn't overlap with that HOB.\r
//\r
- MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r
+ MemoryBase = mPlatformInfoHob.S3Supported && mPlatformInfoHob.SmmSmramRequire ?\r
PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r
PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
MemorySize = LowerMemorySize - MemoryBase;\r
// normal boot permanent PEI RAM. Regarding the S3 boot path, the S3\r
// permanent PEI RAM is located even higher.\r
//\r
- if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {\r
+ if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.Q35SmramAtDefaultSmbase) {\r
ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);\r
}\r
\r
return Status;\r
}\r
\r
-STATIC\r
-VOID\r
-QemuInitializeRamBelow1gb (\r
- VOID\r
- )\r
-{\r
- if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {\r
- AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);\r
- AddReservedMemoryBaseSizeHob (\r
- SMM_DEFAULT_SMBASE,\r
- MCH_DEFAULT_SMBASE_SIZE,\r
- TRUE /* Cacheable */\r
- );\r
- STATIC_ASSERT (\r
- SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,\r
- "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"\r
- );\r
- AddMemoryRangeHob (\r
- SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,\r
- BASE_512KB + BASE_128KB\r
- );\r
- } else {\r
- AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
- }\r
-}\r
-\r
-/**\r
- Peform Memory Detection for QEMU / KVM\r
-\r
-**/\r
-STATIC\r
-VOID\r
-QemuInitializeRam (\r
- VOID\r
- )\r
-{\r
- UINT64 LowerMemorySize;\r
- MTRR_SETTINGS MtrrSettings;\r
- EFI_STATUS Status;\r
-\r
- DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));\r
-\r
- //\r
- // Determine total memory size available\r
- //\r
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
-\r
- if (mBootMode == BOOT_ON_S3_RESUME) {\r
- //\r
- // Create the following memory HOB as an exception on the S3 boot path.\r
- //\r
- // Normally we'd create memory HOBs only on the normal boot path. However,\r
- // CpuMpPei specifically needs such a low-memory HOB on the S3 path as\r
- // well, for "borrowing" a subset of it temporarily, for the AP startup\r
- // vector.\r
- //\r
- // CpuMpPei saves the original contents of the borrowed area in permanent\r
- // PEI RAM, in a backup buffer allocated with the normal PEI services.\r
- // CpuMpPei restores the original contents ("returns" the borrowed area) at\r
- // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before\r
- // transferring control to the OS's wakeup vector in the FACS.\r
- //\r
- // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to\r
- // restore the original contents. Furthermore, we expect all such PEIMs\r
- // (CpuMpPei included) to claim the borrowed areas by producing memory\r
- // allocation HOBs, and to honor preexistent memory allocation HOBs when\r
- // looking for an area to borrow.\r
- //\r
- QemuInitializeRamBelow1gb ();\r
- } else {\r
- //\r
- // Create memory HOBs\r
- //\r
- QemuInitializeRamBelow1gb ();\r
-\r
- if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
- UINT32 TsegSize;\r
-\r
- TsegSize = mQ35TsegMbytes * SIZE_1MB;\r
- AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r
- AddReservedMemoryBaseSizeHob (\r
- LowerMemorySize - TsegSize,\r
- TsegSize,\r
- TRUE\r
- );\r
- } else {\r
- AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
- }\r
-\r
- //\r
- // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM\r
- // entries. Otherwise, create a single memory HOB with the flat >=4GB\r
- // memory size read from the CMOS.\r
- //\r
- Status = ScanOrAdd64BitE820Ram (TRUE, NULL, NULL);\r
- }\r
-\r
- //\r
- // We'd like to keep the following ranges uncached:\r
- // - [640 KB, 1 MB)\r
- // - [LowerMemorySize, 4 GB)\r
- //\r
- // Everything else should be WB. Unfortunately, programming the inverse (ie.\r
- // keeping the default UC, and configuring the complement set of the above as\r
- // WB) is not reliable in general, because the end of the upper RAM can have\r
- // practically any alignment, and we may not have enough variable MTRRs to\r
- // cover it exactly.\r
- //\r
- if (IsMtrrSupported () && (mHostBridgeDevId != CLOUDHV_DEVICE_ID)) {\r
- MtrrGetAllMtrrs (&MtrrSettings);\r
-\r
- //\r
- // MTRRs disabled, fixed MTRRs disabled, default type is uncached\r
- //\r
- ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);\r
- ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);\r
- ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);\r
-\r
- //\r
- // flip default type to writeback\r
- //\r
- SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);\r
- ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);\r
- MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;\r
- MtrrSetAllMtrrs (&MtrrSettings);\r
-\r
- //\r
- // Set memory range from 640KB to 1MB to uncacheable\r
- //\r
- Status = MtrrSetMemoryAttribute (\r
- BASE_512KB + BASE_128KB,\r
- BASE_1MB - (BASE_512KB + BASE_128KB),\r
- CacheUncacheable\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- //\r
- // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI\r
- // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.\r
- //\r
- Status = MtrrSetMemoryAttribute (\r
- mQemuUc32Base,\r
- SIZE_4GB - mQemuUc32Base,\r
- CacheUncacheable\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
-}\r
-\r
/**\r
Publish system RAM and reserve memory regions\r
\r
**/\r
VOID\r
InitializeRamRegions (\r
- VOID\r
+ IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r
)\r
{\r
- QemuInitializeRam ();\r
-\r
- SevInitializeRam ();\r
-\r
- if (mS3Supported && (mBootMode != BOOT_ON_S3_RESUME)) {\r
- //\r
- // This is the memory range that will be used for PEI on S3 resume\r
- //\r
- BuildMemoryAllocationHob (\r
- mS3AcpiReservedMemoryBase,\r
- mS3AcpiReservedMemorySize,\r
- EfiACPIMemoryNVS\r
- );\r
-\r
- //\r
- // Cover the initial RAM area used as stack and temporary PEI heap.\r
- //\r
- // This is reserved as ACPI NVS so it can be used on S3 resume.\r
- //\r
- BuildMemoryAllocationHob (\r
- PcdGet32 (PcdOvmfSecPeiTempRamBase),\r
- PcdGet32 (PcdOvmfSecPeiTempRamSize),\r
- EfiACPIMemoryNVS\r
- );\r
-\r
- //\r
- // SEC stores its table of GUIDed section handlers here.\r
- //\r
- BuildMemoryAllocationHob (\r
- PcdGet64 (PcdGuidedExtractHandlerTableAddress),\r
- PcdGet32 (PcdGuidedExtractHandlerTableSize),\r
- EfiACPIMemoryNVS\r
- );\r
-\r
- #ifdef MDE_CPU_X64\r
- //\r
- // Reserve the initial page tables built by the reset vector code.\r
- //\r
- // Since this memory range will be used by the Reset Vector on S3\r
- // resume, it must be reserved as ACPI NVS.\r
- //\r
- BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase),\r
- (UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize),\r
- EfiACPIMemoryNVS\r
- );\r
-\r
- if (MemEncryptSevEsIsEnabled ()) {\r
- //\r
- // If SEV-ES is enabled, reserve the GHCB-related memory area. This\r
- // includes the extra page table used to break down the 2MB page\r
- // mapping into 4KB page entries where the GHCB resides and the\r
- // GHCB area itself.\r
- //\r
- // Since this memory range will be used by the Reset Vector on S3\r
- // resume, it must be reserved as ACPI NVS.\r
- //\r
- BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableBase),\r
- (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableSize),\r
- EfiACPIMemoryNVS\r
- );\r
- BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBase),\r
- (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbSize),\r
- EfiACPIMemoryNVS\r
- );\r
- BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase),\r
- (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupSize),\r
- EfiACPIMemoryNVS\r
- );\r
- }\r
-\r
- #endif\r
+ if (TdIsEnabled ()) {\r
+ PlatformTdxPublishRamRegions ();\r
+ return;\r
}\r
\r
- if (mBootMode != BOOT_ON_S3_RESUME) {\r
- if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r
- //\r
- // Reserve the lock box storage area\r
- //\r
- // Since this memory range will be used on S3 resume, it must be\r
- // reserved as ACPI NVS.\r
- //\r
- // If S3 is unsupported, then various drivers might still write to the\r
- // LockBox area. We ought to prevent DXE from serving allocation requests\r
- // such that they would overlap the LockBox storage.\r
- //\r
- ZeroMem (\r
- (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)\r
- );\r
- BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
- (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),\r
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r
- );\r
- }\r
-\r
- if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
- UINT32 TsegSize;\r
-\r
- //\r
- // Make sure the TSEG area that we reported as a reserved memory resource\r
- // cannot be used for reserved memory allocations.\r
- //\r
- TsegSize = mQ35TsegMbytes * SIZE_1MB;\r
- BuildMemoryAllocationHob (\r
- GetSystemMemorySizeBelow4gb () - TsegSize,\r
- TsegSize,\r
- EfiReservedMemoryType\r
- );\r
- //\r
- // Similarly, allocate away the (already reserved) SMRAM at the default\r
- // SMBASE, if it exists.\r
- //\r
- if (mQ35SmramAtDefaultSmbase) {\r
- BuildMemoryAllocationHob (\r
- SMM_DEFAULT_SMBASE,\r
- MCH_DEFAULT_SMBASE_SIZE,\r
- EfiReservedMemoryType\r
- );\r
- }\r
- }\r
+ PlatformQemuInitializeRam (PlatformInfoHob);\r
\r
- #ifdef MDE_CPU_X64\r
- if (FixedPcdGet32 (PcdOvmfWorkAreaSize) != 0) {\r
- //\r
- // Reserve the work area.\r
- //\r
- // Since this memory range will be used by the Reset Vector on S3\r
- // resume, it must be reserved as ACPI NVS.\r
- //\r
- // If S3 is unsupported, then various drivers might still write to the\r
- // work area. We ought to prevent DXE from serving allocation requests\r
- // such that they would overlap the work area.\r
- //\r
- BuildMemoryAllocationHob (\r
- (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),\r
- (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),\r
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r
- );\r
- }\r
+ SevInitializeRam ();\r
\r
- #endif\r
- }\r
+ PlatformQemuInitializeRamForS3 (PlatformInfoHob);\r
}\r
projects / mirror_edk2.git / blobdiff