OvmfPkg/ResetVector: cache the SEV status MSR value in workarea

[mirror_edk2.git] / OvmfPkg / ResetVector / ResetVector.nasmb

diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/ResetVector.nasmb
index c5e0fe93abf44df9e0b1bb49f816db35fc918bf8..9421f48189074ee0957a6a9888c772fa9173a3f4 100644 (file)
--- a/OvmfPkg/ResetVector/ResetVector.nasmb
+++ b/OvmfPkg/ResetVector/ResetVector.nasmb
@@ -3,6 +3,7 @@
 ; This file includes all other code files to assemble the reset vector code\r
 ;\r
 ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>\r
 ; SPDX-License-Identifier: BSD-2-Clause-Patent\r
 ;\r
 ;------------------------------------------------------------------------------\r
@@ -46,6 +47,8 @@
 %include "Ia32/SearchForBfvBase.asm"\r
 %include "Ia32/SearchForSecEntry.asm"\r
 \r
+%define WORK_AREA_GUEST_TYPE (FixedPcdGet32 (PcdOvmfWorkAreaBase))\r
+\r
 %ifdef ARCH_X64\r
   #include <AutoGen.h>\r
 \r
@@ -66,15 +69,67 @@
     %error "This implementation inherently depends on PcdOvmfSecGhcbBase not straddling a 2MB boundary"\r
   %endif\r
 \r
+  %define TDX_BFV_RAW_DATA_OFFSET   FixedPcdGet32 (PcdBfvRawDataOffset)\r
+  %define TDX_BFV_RAW_DATA_SIZE     FixedPcdGet32 (PcdBfvRawDataSize)\r
+  %define TDX_BFV_MEMORY_BASE       FixedPcdGet32 (PcdBfvBase)\r
+  %define TDX_BFV_MEMORY_SIZE       FixedPcdGet32 (PcdBfvRawDataSize)\r
+\r
+  %define TDX_CFV_RAW_DATA_OFFSET   FixedPcdGet32 (PcdCfvRawDataOffset)\r
+  %define TDX_CFV_RAW_DATA_SIZE     FixedPcdGet32 (PcdCfvRawDataSize)\r
+  %define TDX_CFV_MEMORY_BASE       FixedPcdGet32 (PcdCfvBase),\r
+  %define TDX_CFV_MEMORY_SIZE       FixedPcdGet32 (PcdCfvRawDataSize),\r
+\r
+  %define TDX_HEAP_STACK_BASE       FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)\r
+  %define TDX_HEAP_STACK_SIZE       FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)\r
+\r
+  %define TDX_HOB_MEMORY_BASE       FixedPcdGet32 (PcdOvmfSecGhcbBase)\r
+  %define TDX_HOB_MEMORY_SIZE       FixedPcdGet32 (PcdOvmfSecGhcbSize)\r
+\r
+  %define TDX_INIT_MEMORY_BASE      FixedPcdGet32 (PcdOvmfWorkAreaBase)\r
+  %define TDX_INIT_MEMORY_SIZE      (FixedPcdGet32 (PcdOvmfWorkAreaSize) + FixedPcdGet32 (PcdOvmfSecGhcbBackupSize))\r
+\r
+  %define OVMF_PAGE_TABLE_BASE      FixedPcdGet32 (PcdOvmfSecPageTablesBase)\r
+  %define OVMF_PAGE_TABLE_SIZE      FixedPcdGet32 (PcdOvmfSecPageTablesSize)\r
+\r
+  %define TDX_WORK_AREA_PGTBL_READY (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 4)\r
+  %define TDX_WORK_AREA_GPAW        (FixedPcdGet32 (PcdOvmfWorkAreaBase) + 8)\r
+\r
   %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))\r
-%include "Ia32/Flat32ToFlat64.asm"\r
 \r
   %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase))\r
   %define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase))\r
   %define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))\r
   %define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase))\r
+  %define SEV_ES_WORK_AREA_SIZE 25\r
+  %define SEV_ES_WORK_AREA_STATUS_MSR (FixedPcdGet32 (PcdSevEsWorkAreaBase))\r
+  %define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)\r
+  %define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 16)\r
+  %define SEV_ES_WORK_AREA_RECEIVED_VC (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 24)\r
   %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))\r
+  %define SEV_SNP_SECRETS_BASE  (FixedPcdGet32 (PcdOvmfSnpSecretsBase))\r
+  %define SEV_SNP_SECRETS_SIZE  (FixedPcdGet32 (PcdOvmfSnpSecretsSize))\r
+  %define CPUID_BASE  (FixedPcdGet32 (PcdOvmfCpuidBase))\r
+  %define CPUID_SIZE  (FixedPcdGet32 (PcdOvmfCpuidSize))\r
+  %define SNP_SEC_MEM_BASE_DESC_1 (FixedPcdGet32 (PcdOvmfSecPageTablesBase))\r
+  %define SNP_SEC_MEM_SIZE_DESC_1 (FixedPcdGet32 (PcdOvmfSecGhcbBase) - SNP_SEC_MEM_BASE_DESC_1)\r
+  ;\r
+  ; The PcdOvmfSecGhcbBase reserves two GHCB pages. The first page is used\r
+  ; as GHCB shared page and second is used for bookkeeping to support the\r
+  ; nested GHCB in SEC phase. The bookkeeping page is mapped private. The VMM\r
+  ; does not need to validate the shared page but it need to validate the\r
+  ; bookkeeping page.\r
+  ;\r
+  %define SNP_SEC_MEM_BASE_DESC_2 (GHCB_BASE + 0x1000)\r
+  %define SNP_SEC_MEM_SIZE_DESC_2 (SEV_SNP_SECRETS_BASE - SNP_SEC_MEM_BASE_DESC_2)\r
+  %define SNP_SEC_MEM_BASE_DESC_3 (CPUID_BASE + CPUID_SIZE)\r
+  %define SNP_SEC_MEM_SIZE_DESC_3 (FixedPcdGet32 (PcdOvmfPeiMemFvBase) - SNP_SEC_MEM_BASE_DESC_3)\r
+\r
+%include "X64/IntelTdxMetadata.asm"\r
+%include "Ia32/Flat32ToFlat64.asm"\r
+%include "Ia32/AmdSev.asm"\r
 %include "Ia32/PageTables64.asm"\r
+%include "Ia32/IntelTdx.asm"\r
+%include "X64/OvmfSevMetadata.asm"\r
 %endif\r
 \r
 %include "Ia16/Real16ToFlat32.asm"\r
@@ -85,5 +140,7 @@
   %define SEV_ES_AP_RESET_IP  FixedPcdGet32 (PcdSevEsWorkAreaBase)\r
   %define SEV_LAUNCH_SECRET_BASE  FixedPcdGet32 (PcdSevLaunchSecretBase)\r
   %define SEV_LAUNCH_SECRET_SIZE  FixedPcdGet32 (PcdSevLaunchSecretSize)\r
+  %define SEV_FW_HASH_BLOCK_BASE  FixedPcdGet32 (PcdQemuHashTableBase)\r
+  %define SEV_FW_HASH_BLOCK_SIZE  FixedPcdGet32 (PcdQemuHashTableSize)\r
 %include "Ia16/ResetVectorVtf0.asm"\r
 \r