OvmfPkg/ResetVector: cache the SEV status MSR value in workarea

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3582

In order to probe the SEV feature the BaseMemEncryptLib and Reset vector
reads the SEV_STATUS MSR. Cache the value on the first read in the
workarea. In the next patches the value saved in the workarea will
be used by the BaseMemEncryptLib. This not only eliminates the extra
MSR reads it also helps cleaning up the code in BaseMemEncryptLib.

Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Acked-by: Jiewen Yao <jiewen.yao@intel.com>

diff --git a/OvmfPkg/Include/WorkArea.h b/OvmfPkg/Include/WorkArea.h
index ce60d97aa8866d2825bafc878b928667fea45414..d982e026def774bfd61f7c7792874e94a1d62513 100644 (file)
--- a/OvmfPkg/Include/WorkArea.h
+++ b/OvmfPkg/Include/WorkArea.h
@@ -46,12 +46,20 @@ typedef struct _CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER {
 // any changes must stay in sync with its usage.\r
 //\r
 typedef struct _SEC_SEV_ES_WORK_AREA {\r
-  UINT8     SevEsEnabled;\r
-  UINT8     Reserved1[7];\r
+  //\r
+  // Hold the SevStatus MSR value read by OvmfPkg/ResetVector/Ia32/AmdSev.c\r
+  //\r
+  UINT64    SevStatusMsrValue;\r
 \r
   UINT64    RandomData;\r
 \r
   UINT64    EncryptionMask;\r
+\r
+  //\r
+  // Indicator that the VC handler is called. It is used during the SevFeature\r
+  // detection in OvmfPkg/ResetVector/Ia32/AmdSev.c\r
+  //\r
+  UINT8     ReceivedVc;\r
 } SEC_SEV_ES_WORK_AREA;\r
 \r
 //\r

diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
index 1f827da3b92909221e3407b1fb388c8fb3a62bd1..864d68385342c7d49bb41154b4c0b8c2038a479b 100644 (file)
--- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm
+++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm
@@ -157,8 +157,9 @@ SevClearPageEncMaskForGhcbPage:
     jnz       SevClearPageEncMaskForGhcbPageExit\r
 \r
     ; Check if SEV-ES is enabled\r
-    cmp       byte[SEV_ES_WORK_AREA], 1\r
-    jnz       SevClearPageEncMaskForGhcbPageExit\r
+    mov       ecx, 1\r
+    bt        [SEV_ES_WORK_AREA_STATUS_MSR], ecx\r
+    jnc       SevClearPageEncMaskForGhcbPageExit\r
 \r
     ;\r
     ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted.\r
@@ -219,12 +220,16 @@ GetSevCBitMaskAbove31Exit:
 ; If SEV is disabled then EAX will be zero.\r
 ;\r
 CheckSevFeatures:\r
-    ; Set the first byte of the workarea to zero to communicate to the SEC\r
-    ; phase that SEV-ES is not enabled. If SEV-ES is enabled, the CPUID\r
-    ; instruction will trigger a #VC exception where the first byte of the\r
-    ; workarea will be set to one or, if CPUID is not being intercepted,\r
-    ; the MSR check below will set the first byte of the workarea to one.\r
-    mov     byte[SEV_ES_WORK_AREA], 0\r
+    ;\r
+    ; Clear the workarea, if SEV is enabled then later part of routine\r
+    ; will populate the workarea fields.\r
+    ;\r
+    mov    ecx, SEV_ES_WORK_AREA_SIZE\r
+    mov    eax, SEV_ES_WORK_AREA\r
+ClearSevEsWorkArea:\r
+    mov    byte [eax], 0\r
+    inc    eax\r
+    loop   ClearSevEsWorkArea\r
 \r
     ;\r
     ; Set up exception handlers to check for SEV-ES\r
@@ -265,6 +270,10 @@ CheckSevFeatures:
     ; Set the work area header to indicate that the SEV is enabled\r
     mov     byte[WORK_AREA_GUEST_TYPE], 1\r
 \r
+    ; Save the SevStatus MSR value in the workarea\r
+    mov     [SEV_ES_WORK_AREA_STATUS_MSR], eax\r
+    mov     [SEV_ES_WORK_AREA_STATUS_MSR + 4], edx\r
+\r
     ; Check for SEV-ES memory encryption feature:\r
     ; CPUID  Fn8000_001F[EAX] - Bit 3\r
     ;   CPUID raises a #VC exception if running as an SEV-ES guest\r
@@ -280,10 +289,6 @@ CheckSevFeatures:
     bt        eax, 1\r
     jnc       GetSevEncBit\r
 \r
-    ; Set the first byte of the workarea to one to communicate to the SEC\r
-    ; phase that SEV-ES is enabled.\r
-    mov       byte[SEV_ES_WORK_AREA], 1\r
-\r
 GetSevEncBit:\r
     ; Get pte bit position to enable memory encryption\r
     ; CPUID Fn8000_001F[EBX] - Bits 5:0\r
@@ -313,7 +318,10 @@ NoSev:
     ;\r
     ; Perform an SEV-ES sanity check by seeing if a #VC exception occurred.\r
     ;\r
-    cmp       byte[SEV_ES_WORK_AREA], 0\r
+    ; If SEV-ES is enabled, the CPUID instruction will trigger a #VC exception\r
+    ; where the RECEIVED_VC offset in the workarea will be set to one.\r
+    ;\r
+    cmp       byte[SEV_ES_WORK_AREA_RECEIVED_VC], 0\r
     jz        NoSevPass\r
 \r
     ;\r
@@ -407,9 +415,9 @@ SevEsIdtVmmComm:
     ; If we're here, then we are an SEV-ES guest and this\r
     ; was triggered by a CPUID instruction\r
     ;\r
-    ; Set the first byte of the workarea to one to communicate that\r
+    ; Set the recievedVc field in the workarea to communicate that\r
     ; a #VC was taken.\r
-    mov     byte[SEV_ES_WORK_AREA], 1\r
+    mov     byte[SEV_ES_WORK_AREA_RECEIVED_VC], 1\r
 \r
     pop     ecx                     ; Error code\r
     cmp     ecx, 0x72               ; Be sure it was CPUID\r

diff --git a/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm b/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm
index eb3546668ef82a3fa55276fed74037c2c21177a9..c5c683ebed3ed82bf22ba2ad03151ba131ed1d96 100644 (file)
--- a/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm
+++ b/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm
@@ -42,7 +42,8 @@ Transition32FlatTo64Flat:
     ;\r
     xor     ebx, ebx\r
 \r
-    cmp     byte[SEV_ES_WORK_AREA], 0\r
+    mov     ecx, 1\r
+    bt      [SEV_ES_WORK_AREA_STATUS_MSR], ecx\r
     jz      EnablePaging\r
 \r
     ;\r

diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/ResetVector.nasmb
index cc364748b5925c9bde013ac972b1ab3ca8f72fb8..9421f48189074ee0957a6a9888c772fa9173a3f4 100644 (file)
--- a/OvmfPkg/ResetVector/ResetVector.nasmb
+++ b/OvmfPkg/ResetVector/ResetVector.nasmb
@@ -100,8 +100,11 @@
   %define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase))\r
   %define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))\r
   %define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase))\r
+  %define SEV_ES_WORK_AREA_SIZE 25\r
+  %define SEV_ES_WORK_AREA_STATUS_MSR (FixedPcdGet32 (PcdSevEsWorkAreaBase))\r
   %define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)\r
   %define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 16)\r
+  %define SEV_ES_WORK_AREA_RECEIVED_VC (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 24)\r
   %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))\r
   %define SEV_SNP_SECRETS_BASE  (FixedPcdGet32 (PcdOvmfSnpSecretsBase))\r
   %define SEV_SNP_SECRETS_SIZE  (FixedPcdGet32 (PcdOvmfSnpSecretsSize))\r

diff --git a/OvmfPkg/Sec/AmdSev.c b/OvmfPkg/Sec/AmdSev.c
index 499d0c27d8fa03b808c3e58ede1670806e2a5171..d8fd35650d7d41ad9657c0c32760c94caccdbe46 100644 (file)
--- a/OvmfPkg/Sec/AmdSev.c
+++ b/OvmfPkg/Sec/AmdSev.c
@@ -278,7 +278,7 @@ SevEsIsEnabled (
 \r
   SevEsWorkArea = (SEC_SEV_ES_WORK_AREA *)FixedPcdGet32 (PcdSevEsWorkAreaBase);\r
 \r
-  return (SevEsWorkArea->SevEsEnabled != 0);\r
+  return ((SevEsWorkArea->SevStatusMsrValue & BIT1) != 0);\r
 }\r
 \r
 /**\r