//\r
// Set TSEG Memory Base.\r
//\r
+ InitQ35TsegMbytes ();\r
PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB),\r
- (TopOfLowRamMb - FixedPcdGet8 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHIFT);\r
+ (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT);\r
\r
//\r
// Set TSEG size, and disable TSEG visibility outside of SMM. Note that the\r
// *restricted* to SMM.\r
//\r
EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;\r
- EsmramcVal |= FixedPcdGet8 (PcdQ35TsegMbytes) == 8 ? MCH_ESMRAMC_TSEG_8MB :\r
- FixedPcdGet8 (PcdQ35TsegMbytes) == 2 ? MCH_ESMRAMC_TSEG_2MB :\r
- MCH_ESMRAMC_TSEG_1MB;\r
+ EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :\r
+ mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :\r
+ mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :\r
+ MCH_ESMRAMC_TSEG_EXT;\r
EsmramcVal |= MCH_ESMRAMC_T_EN;\r
PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);\r
\r