ArmPkg/BdsLib: Fixed line ending

[mirror_edk2.git] / PcAtChipsetPkg / PciHostBridgeDxe / PciHostBridge.c

diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
index f14700e3c4c1e619ac2274900fb6da16e248b1f5..2f6ef68f1dcc742752ab6d89adea9f095d69c8fd 100644 (file)
--- a/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
+++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
@@ -1,7 +1,7 @@
 /** @file\r
   Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation\r
 \r
-Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials are\r
 licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -18,7 +18,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 // Hard code: Root Bridge Number within the host bridge\r
 //            Root Bridge's attribute\r
 //            Root Bridge's device path\r
-//            Root Bridge's resource appeture\r
+//            Root Bridge's resource aperture\r
 //\r
 UINTN RootBridgeNumber[1] = { 1 };\r
 \r
@@ -52,7 +52,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
   }\r
 };\r
 \r
-PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[1][1] = {\r
+PCI_ROOT_BRIDGE_RESOURCE_APERTURE  mResAperture[1][1] = {\r
   {{0, 0xff, 0x80000000, 0xffffffff, 0, 0xffff}}\r
 };\r
 \r
@@ -145,7 +145,7 @@ InitializePciHostBridge (
         &PrivateData->Io, \r
         HostBridge->HostBridgeHandle, \r
         RootBridgeAttribute[Loop1][Loop2], \r
-        &mResAppeture[Loop1][Loop2]\r
+        &mResAperture[Loop1][Loop2]\r
         );\r
     \r
       Status = gBS->InstallMultipleProtocolInterfaces(\r
@@ -281,12 +281,14 @@ NotifyPhase(
     }  \r
     break;\r
 \r
+  case EfiPciHostBridgeEndEnumeration:\r
+    break;\r
+\r
   case EfiPciHostBridgeBeginBusAllocation:\r
     //\r
     // No specific action is required here, can perform any chipset specific programing\r
     //\r
     HostBridgeInstance->CanRestarted = FALSE;\r
-    return EFI_SUCCESS;\r
     break;\r
 \r
   case EfiPciHostBridgeEndBusAllocation:\r
@@ -294,7 +296,6 @@ NotifyPhase(
     // No specific action is required here, can perform any chipset specific programing\r
     //\r
     //HostBridgeInstance->CanRestarted = FALSE;\r
-    return EFI_SUCCESS;\r
     break;\r
 \r
   case EfiPciHostBridgeBeginResourceAllocation:\r
@@ -302,7 +303,6 @@ NotifyPhase(
     // No specific action is required here, can perform any chipset specific programing\r
     //\r
     //HostBridgeInstance->CanRestarted = FALSE;\r
-    return EFI_SUCCESS;\r
     break;\r
 \r
   case EfiPciHostBridgeAllocateResources:\r
@@ -472,7 +472,6 @@ NotifyPhase(
     HostBridgeInstance->ResourceSubmited = FALSE;\r
     HostBridgeInstance->CanRestarted     = TRUE;      \r
     return ReturnStatus;\r
-    break;\r
 \r
   case EfiPciHostBridgeEndResourceAllocation:\r
     HostBridgeInstance->CanRestarted = FALSE;\r
@@ -480,7 +479,7 @@ NotifyPhase(
 \r
   default:\r
     return EFI_INVALID_PARAMETER;\r
-  }; // end switch\r
+  }\r
   \r
   return EFI_SUCCESS;  \r
 }\r